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修复语法错误

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RuigeLee
2025-09-05 19:30:35 +08:00
parent 4bc5e2927e
commit ac118289b2
2 changed files with 4 additions and 13 deletions
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8
src/main/scala/backBoard/shin/MstSlvSwitch.scala
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@@ -511,7 +511,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
}
trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
val isDwUpEx = interface.io.cReg.dwupEx(15,8) === "h58".U && interface.io.cReg.dwupEx.extract(0)
val isDwUpEx = interface.io.cReg.dwupEx.extract(0)
when( ~isDwUpEx ){ //未交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
@@ -582,7 +582,7 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
}
trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
val isUsing8b10b = interface.io.cReg.b8b4Sel(15,8) === "h59".U && interface.io.cReg.b8b4Sel.extract(0)
val isUsing8b10b = interface.io.cReg.b8b4Sel.extract(0)
when( isUsing8b10b ){
b8b10DownEncoder.io <> io.downCDROut.encode
@@ -612,8 +612,8 @@ trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
}
trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
val cdrSelB = interface.io.cReg.cdrParam(15,8) === "h60".U && interface.io.cReg.b8b4Sel(7,0) === 1.U
val cdrSelC = interface.io.cReg.cdrParam(15,8) === "h60".U && interface.io.cReg.b8b4Sel(7,0) === 2.U
val cdrSelB = interface.io.cReg.cdrParam === 1.U
val cdrSelC = interface.io.cReg.cdrParam === 2.U
val cdrSelA = ~cdrSelB & ~cdrSelC
}