From ac118289b2362ae9e57b3de15cbb7b05361a5c2c Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 5 Sep 2025 19:30:35 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E8=AF=AD=E6=B3=95=E9=94=99?= =?UTF-8?q?=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 9 --------- src/main/scala/backBoard/shin/MstSlvSwitch.scala | 8 ++++---- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 254c703..e2d8740 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -298,15 +298,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === ("h48".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 ) }) ++ - - ((0 until 2).map{ i => - (addr === ("h4c".U(16.W) + i.U) ) -> cReg.b8b4Sel( 8*i+7,8*i+0 ) - }) ++ - - ((0 until 2).map{ i => - (addr === ("h4e".U(16.W) + i.U) ) -> cReg.cdrParam( 8*i+7,8*i+0 ) - }) ++ - Seq( (addr === "h4a".U ) -> cReg.dwupEx, (addr === "h4c".U ) -> cReg.b8b4Sel, diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 9814eae..f0efcdc 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -511,7 +511,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => } trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase => - val isDwUpEx = interface.io.cReg.dwupEx(15,8) === "h58".U && interface.io.cReg.dwupEx.extract(0) + val isDwUpEx = interface.io.cReg.dwupEx.extract(0) when( ~isDwUpEx ){ //未交叉 when( interface.io.cReg.modeSel === false.B ){ //slave @@ -582,7 +582,7 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase => } trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase => - val isUsing8b10b = interface.io.cReg.b8b4Sel(15,8) === "h59".U && interface.io.cReg.b8b4Sel.extract(0) + val isUsing8b10b = interface.io.cReg.b8b4Sel.extract(0) when( isUsing8b10b ){ b8b10DownEncoder.io <> io.downCDROut.encode @@ -612,8 +612,8 @@ trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase => } trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase => - val cdrSelB = interface.io.cReg.cdrParam(15,8) === "h60".U && interface.io.cReg.b8b4Sel(7,0) === 1.U - val cdrSelC = interface.io.cReg.cdrParam(15,8) === "h60".U && interface.io.cReg.b8b4Sel(7,0) === 2.U + val cdrSelB = interface.io.cReg.cdrParam === 1.U + val cdrSelC = interface.io.cReg.cdrParam === 2.U val cdrSelA = ~cdrSelB & ~cdrSelC }