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ebus拉到顶层

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This commit is contained in:
RuigeLee
2024-05-16 20:02:03 +08:00
parent 45e46b2d46
commit aaf932ffd4
8 changed files with 300 additions and 305 deletions
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115
src/main/verilog/backBoardMstTop.v
View File

@@ -122,41 +122,106 @@ CLKDIV Inst5_CLKDIVC(
.CLKOUT (clk_10m_a)
);
wire frame_info_update_en;
wire [7:0] slave_type_num;
wire [7:0] slave_data_length;
wire tx_start;
wire slave_link_num_valid;
wire [6:0] slave_link_num;
wire downstream_busy;
wire upstream_crc_valid;
wire closed_loop_err;
wire [6:0] link_err_location;
wire upstream_cdr_err;
wire upstream_crc_err;
wire [7:0] tx_data_in;
wire tx_data_ready;
wire [7:0] rx_data_out;
wire rx_data_valid;
lvds_bus_master_top i_lvds_bus_master(
.rst_n(rst_n),
.reset_calib(reset_calib),
.oser_pclk(clk_10m_a),
.oser_fclk(clk_50m_a),
.ides_pclk(clk_100m_a),
.ides_fclk(clk_400m_a),
.lvds_down_dout(lvds_down_dout),
.lvds_up_din(lvds_up_din),
.frame_info_update_en(frame_info_update_en),
.slave_type_num(slave_type_num),
.slave_data_length(slave_data_length),
.slave_link_num_valid(slave_link_num_valid),
.slave_link_num(slave_link_num),
.tx_start(tx_start),
.tx_data_in(tx_data_in),
.tx_data_ready(tx_data_ready),
.downstream_busy(downstream_busy),
.rx_data_out(rx_data_out),
.rx_data_valid(rx_data_valid),
.upstream_crc_valid(upstream_crc_valid),
.upstream_crc_err(upstream_crc_err),
.upstream_crc_err_count(),
.upstream_cdr_err(upstream_cdr_err),
.closed_loop_err(closed_loop_err),
.link_err_location(link_err_location),
.test_downstream_tx_en(),
.test_downstream_tx_8b_data(),
.test_downstream_tx_10b_data(),
.test_upstream_rx_busy(),
.test_upstream_rx_10b_data(),
.test_upstream_rx_8b_data()
);
BackBoardMst i_BackBoardMst(
.io_FSMC_ADIn (io_FSMC_ADIn),
.io_FSMC_ADOut(io_FSMC_ADOut),
.io_FSMC_ADOEn(io_FSMC_ADOEn),
.io_FSMC_csn(io_FSMC_csn),
.io_FSMC_rdn(io_FSMC_rdn),
.io_FSMC_wrn(io_FSMC_wrn),
.io_FSMC_advn(io_FSMC_advn),
.io_FSMC_ADIn (io_FSMC_ADIn),
.io_FSMC_ADOut(io_FSMC_ADOut),
.io_FSMC_ADOEn(io_FSMC_ADOEn),
.io_FSMC_csn(io_FSMC_csn),
.io_FSMC_rdn(io_FSMC_rdn),
.io_FSMC_wrn(io_FSMC_wrn),
.io_FSMC_advn(io_FSMC_advn),
// .io_FSMC_ADIn ('d0),
// .io_FSMC_ADOut(),
// .io_FSMC_ADOEn(),
// .io_FSMC_csn(1'b1),
// .io_FSMC_rdn(1'b1),
// .io_FSMC_wrn(1'b1),
// .io_FSMC_advn(1'b1),
.reset(~rst_n),
.clock(clk_10m_a),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.reset(~rst_n),
.clock(clk_10m_a),
.io_reset_calib(reset_calib),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_interrupt(interrupt),
.io_testIO(testIO),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din),
.io_lvdsMst_frame_info_update_en(frame_info_update_en),
.io_lvdsMst_slave_type_num(slave_type_num),
.io_lvdsMst_slave_data_length(slave_data_length),
.io_lvdsMst_tx_start(tx_start),
.io_lvdsMst_slave_link_num_valid(slave_link_num_valid),
.io_lvdsMst_slave_link_num(slave_link_num),
.io_lvdsMst_downstream_busy(downstream_busy),
.io_lvdsMst_upstream_crc_valid(upstream_crc_valid),
.io_lvdsMst_closed_loop_err(closed_loop_err),
.io_lvdsMst_link_err_location(link_err_location),
.io_lvdsMst_upstream_cdr_err(upstream_cdr_err),
.io_lvdsMst_upstream_crc_err(upstream_crc_err),
.io_lvdsMst_tx_data_in(tx_data_in),
.io_lvdsMst_tx_data_ready(tx_data_ready),
.io_lvdsMst_rx_data_out(rx_data_out),
.io_lvdsMst_rx_data_valid(rx_data_valid)
.io_interrupt(interrupt),
.io_testIO(testIO)
);

172
src/main/verilog/backBoardSlvTop.v
View File

@@ -1,172 +0,0 @@
module slave_top(
input resetn,
input clock,
input lvds_up_din_p,
input lvds_up_din_n,
output lvds_up_dout_p,
output lvds_up_dout_n,
input lvds_down_din_p,
input lvds_down_din_n,
output lvds_down_dout_p,
output lvds_down_dout_n,
// inout [31:0] digitalIO
output [15:0] digitalIO
);
wire clk_400m;
wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;
wire lock_o;
wire reset_stop;
wire reset_calib;
reg rst_n;
reg rstn_d;
wire [31:0] in;
wire [31:0] out;
wire [31:0] oe;
always@(posedge clk_10m_a) begin
rstn_d <= resetn;
rst_n <= rstn_d;
end
Gowin_PLLO Gowin_PLLO(
.lock(lock_o),
.clkouta(clk_400m),
.clkin(clock)
);
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
.OB(lvds_down_dout_n),
.I(lvds_down_dout)
);
TLVDS_IBUF lvds_downstream_in(
.O(lvds_down_din),
.I(lvds_down_din_p),
.IB(lvds_down_din_n)
);
TLVDS_OBUF lvds_upstream_out(
.O(lvds_up_dout_p),
.OB(lvds_up_dout_n),
.I(lvds_up_dout)
);
TLVDS_IBUF lvds_upstream_in(
.O(lvds_up_din),
.I(lvds_up_din_p),
.IB(lvds_up_din_n)
);
DHCEN dhcen_inst2 (
.CLKIN(clk_400m),
.CE(reset_stop),
.CLKOUT(clk_400m_a)
);
//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
.rst_n(rst_n),
.pll_lock(lock_o), // trigged by PLL Lock
.reset_stop(reset_stop), // for DHCEN CE
.reset_calib(reset_calib), // for IDES and CLKDIV reset
.set_calib(),
.ready()
);
defparam Inst4_CLKDIVC.DIV_MODE="4";
defparam Inst4_CLKDIVC.GSREN="false";
CLKDIV Inst4_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_400m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_100m_a)
);
defparam Inst2_CLKDIVC.DIV_MODE="2";
defparam Inst2_CLKDIVC.GSREN="false";
CLKDIV Inst2_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_100m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_50m_a)
);
defparam Inst5_CLKDIVC.DIV_MODE="5";
defparam Inst5_CLKDIVC.GSREN="false";
CLKDIV Inst5_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_50m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_10m_a)
);
// generate
// for( genvar i = 0; i < 32; i = i + 1 ) begin
// IOBUF uut(
// .O(in[i]),
// .IO(digitalIO[i]),
// .I(out[i]),
// .OEN(~oe[i])
// );
// end
// endgenerate
assign digitalIO = out[15:0];
assign in = 32'hAA55AA55;
BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO(
.reset(~rst_n),
.clock(clk_10m_a),
.io_reset_calib(reset_calib),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din),
.io_lvds_up_dout(lvds_up_dout),
.in(in),
.out(out),
.oe(oe)
);
endmodule

82
src/main/verilog/di16_top.v
View File

@@ -2,7 +2,8 @@
module di16_top(
input clock,
input clock,
input resetn,
input lvds_up_din_p,
input lvds_up_din_n,
@@ -16,14 +17,13 @@ module di16_top(
output isOnline,
input isLast,
input DCIn,
output LED_PR,
input [15:0] in
);
wire resetn = 1'b1;
wire DCIn = 1'b0;
wire clk_400m;
wire clk_400m_a;
@@ -130,19 +130,63 @@ CLKDIV Inst5_CLKDIVC(
.CLKOUT (clk_10m_a)
);
wire [7:0] downstream_rx_data_out;
wire downstream_rx_data_valid;
wire downstream_rx_crc_valid;
wire downstream_rx_crc_err;
wire upstream_tx_data_ready;
wire [7:0] upstream_tx_data_in;
wire downstream_rx_cdr_err;
wire upstream_rx_cdr_err;
lvds_bus_slave_top i_lvds_bus_slave(
.rst_n(rst_n),
.reset_calib(reset_calib),
.oser_pclk(clk_10m_a),
.oser_fclk(clk_50m_a),
.ides_pclk(clk_100m_a),
.ides_fclk(clk_400m_a),
.lvds_down_din(lvds_down_din),
.lvds_down_dout(lvds_down_dout),
.lvds_up_din(lvds_up_din),
.lvds_up_dout(lvds_up_dout),
.downstream_rx_data_valid(downstream_rx_data_valid),
.downstream_rx_unicast_pkg_valid(),
.downstream_rx_data_out(downstream_rx_data_out),
.downstream_rx_crc_valid(downstream_rx_crc_valid),
.downstream_rx_crc_err(downstream_rx_crc_err),
.downstream_rx_crc_err_counter(),
.downstream_rx_cdr_err(downstream_rx_cdr_err),
.downstream_sync(),
.upstream_tx_data_ready(upstream_tx_data_ready),
.upstream_tx_unicast_pkg_ready(),
.upstream_tx_data_in(upstream_tx_data_in),
.upstream_rx_crc_valid(),
.upstream_rx_crc_err(),
.upstream_rx_crc_err_counter(),
.upstream_rx_cdr_err(upstream_rx_cdr_err),
.local_slave_id(),
.test_downstream_rx_10b_data(),
.test_downstream_rx_8b_data(),
.test_downstream_rx_state_machine(),
.test_downstream_tx_en(),
.test_downstream_tx_8b_data(),
.test_downstream_tx_10b_data(),
.test_upstream_rx_10b_data(),
.test_upstream_rx_8b_data(),
.test_upstream_rx_state_machine(),
.test_upstream_tx_en(),
.test_upstream_tx_8b_data(),
.test_upstream_tx_10b_data()
);
DIn16 i_din16(
.reset(~rst_n),
.clock(clk_10m_a),
.io_reset_calib(reset_calib),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din),
.io_lvds_up_dout(lvds_up_dout),
.io_isOnline(isOnline),
.io_isLast(isLast),
@@ -152,10 +196,18 @@ DIn16 i_din16(
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION),
// .param_batchID(`BATCHID),
.param_serial(`SERIAL),
.LED_PR(LED_PR),
.in(in)
.in(in),
.io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
.io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),
.io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid),
.io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err),
.io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready),
.io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in),
.io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
.io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err)
);
endmodule

84
src/main/verilog/do16_top.v
View File

@@ -2,8 +2,8 @@
module do16_top(
input clock,
input clock,
input resetn,
input lvds_up_din_p,
input lvds_up_din_n,
@@ -17,7 +17,7 @@ module do16_top(
output isOnline,
input isLast,
input DCIn,
output LED_PR,
output [15:0] out,
@@ -26,7 +26,7 @@ module do16_top(
);
wire resetn = 1'b1;
wire DCIn = 1'b0;
wire clk_400m;
wire clk_400m_a;
@@ -134,19 +134,64 @@ CLKDIV Inst5_CLKDIVC(
.CLKOUT (clk_10m_a)
);
wire [7:0] downstream_rx_data_out;
wire downstream_rx_data_valid;
wire downstream_rx_crc_valid;
wire downstream_rx_crc_err;
wire upstream_tx_data_ready;
wire [7:0] upstream_tx_data_in;
wire downstream_rx_cdr_err;
wire upstream_rx_cdr_err;
lvds_bus_slave_top i_lvds_bus_slave(
.rst_n(rst_n),
.reset_calib(reset_calib),
.oser_pclk(clk_10m_a),
.oser_fclk(clk_50m_a),
.ides_pclk(clk_100m_a),
.ides_fclk(clk_400m_a),
.lvds_down_din(lvds_down_din),
.lvds_down_dout(lvds_down_dout),
.lvds_up_din(lvds_up_din),
.lvds_up_dout(lvds_up_dout),
.downstream_rx_data_valid(downstream_rx_data_valid),
.downstream_rx_unicast_pkg_valid(),
.downstream_rx_data_out(downstream_rx_data_out),
.downstream_rx_crc_valid(downstream_rx_crc_valid),
.downstream_rx_crc_err(downstream_rx_crc_err),
.downstream_rx_crc_err_counter(),
.downstream_rx_cdr_err(downstream_rx_cdr_err),
.downstream_sync(),
.upstream_tx_data_ready(upstream_tx_data_ready),
.upstream_tx_unicast_pkg_ready(),
.upstream_tx_data_in(upstream_tx_data_in),
.upstream_rx_crc_valid(),
.upstream_rx_crc_err(),
.upstream_rx_crc_err_counter(),
.upstream_rx_cdr_err(upstream_rx_cdr_err),
.local_slave_id(),
.test_downstream_rx_10b_data(),
.test_downstream_rx_8b_data(),
.test_downstream_rx_state_machine(),
.test_downstream_tx_en(),
.test_downstream_tx_8b_data(),
.test_downstream_tx_10b_data(),
.test_upstream_rx_10b_data(),
.test_upstream_rx_8b_data(),
.test_upstream_rx_state_machine(),
.test_upstream_tx_en(),
.test_upstream_tx_8b_data(),
.test_upstream_tx_10b_data()
);
DOut16 i_dout16(
.reset(~rst_n),
.clock(clk_10m_a),
.io_reset_calib(reset_calib),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din),
.io_lvds_up_dout(lvds_up_dout),
.io_isOnline(isOnline),
.io_isLast(isLast),
@@ -161,7 +206,16 @@ DOut16 i_dout16(
.LED_PR(LED_PR),
.out(out),
.flt_0(flt_0),
.flt_1(flt_1)
.flt_1(flt_1),
.io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
.io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),
.io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid),
.io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err),
.io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready),
.io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in),
.io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
.io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err)
);
endmodule