diff --git a/Makefile b/Makefile index 2c5ebba..a044930 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,6 @@ back: rm -f ./generated/* sbt "test:runMain test.testModule" cp ./src/main/verilog/backBoardMstTop.v ./generated/ - # cp ./src/main/verilog/backBoardSlvTop.v ./generated/ cp ./src/main/verilog/oser_rst.v ./generated/ cp ./src/main/verilog/di16_top.v ./generated/ cp ./src/main/verilog/do16_top.v ./generated/ diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index 9f7d93b..4d46362 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -17,29 +17,52 @@ class FSMC_Port_Bundle extends Bundle{ val advn = Input(Bool()) } +class LVDS_MST_Bundle extends Bundle{ + val frame_info_update_en = Output(Bool()) + val slave_type_num = Output(UInt(8.W)) + val slave_data_length = Output(UInt(8.W)) + val tx_start = Output(Bool()) + + val slave_link_num_valid = Input(Bool()) + val slave_link_num = Input(UInt(7.W)) + + val downstream_busy = Input(Bool()) + val upstream_crc_valid = Input(Bool()) + + val closed_loop_err = Input(Bool()) + val link_err_location = Input(UInt(7.W)) + + val upstream_cdr_err = Input(Bool()) + val upstream_crc_err = Input(Bool()) + + val tx_data_ready = Input(Bool()) + val tx_data_in = Output(UInt(8.W)) + val rx_data_valid = Input(Bool()) + val rx_data_out = Input(UInt(8.W)) +} + + class BackBoardMstIO extends Bundle{ val FSMC = new FSMC_Port_Bundle -val reset_calib = Input(Bool()) val oser_pclk = Input(Bool()) //10M val oser_fclk = Input(Bool()) //50M - val ides_pclk = Input(Bool()) //100M + val ides_pclk = Input(Bool()) //100M val ides_fclk = Input(Bool()) //400M - val lvds_down_dout = Output(Bool()) - val lvds_up_din = Input(Bool()) val interrupt = Output(Bool()) val testIO = Input(Bool()) + val lvdsMst = new LVDS_MST_Bundle + } class BackBoardMstBase extends Module{ //10M val io: BackBoardMstIO = IO(new BackBoardMstIO) - val lvdsMst = Module(new Lvds_Bus_Master) val mirrorDown = Module(new MirrorSRAMDown()) val mirrorUp = Module(new MirrorSRAMUp()) val mirrorReg = Module(new MirrorSRAMDP()) @@ -61,16 +84,6 @@ class BackBoardMstBase extends Module{ //10M val interrupt = RegInit(false.B); io.interrupt := interrupt val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1 - lvdsMst.io.rst_n := ~reset.asBool - lvdsMst.io.reset_calib := io.reset_calib - lvdsMst.io.oser_pclk := io.oser_pclk - lvdsMst.io.oser_fclk := io.oser_fclk - lvdsMst.io.ides_pclk := io.ides_pclk - lvdsMst.io.ides_fclk := io.ides_fclk - - io.lvds_down_dout := lvdsMst.io.lvds_down_dout - lvdsMst.io.lvds_up_din := io.lvds_up_din - @@ -160,10 +173,10 @@ with BackBoardMstFSMC val tx_start = RegInit(false.B) - lvdsMst.io.frame_info_update_en := frame_info_update_en - lvdsMst.io.slave_type_num := slave_type_num - lvdsMst.io.slave_data_length := slaveDataLength - lvdsMst.io.tx_start := tx_start + io.lvdsMst.frame_info_update_en := frame_info_update_en + io.lvdsMst.slave_type_num := slave_type_num + io.lvdsMst.slave_data_length := slaveDataLength + io.lvdsMst.tx_start := tx_start val stateCur = RegInit(15.U(4.W)) @@ -231,12 +244,12 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase => tx_start := false.B timeoutCnt := timeoutCnt + 1.U - when( lvdsMst.io.slave_link_num_valid ){ + when( io.lvdsMst.slave_link_num_valid ){ stateCur := 6.U //linkNum mirrorReg.io.addrB := 5.U - mirrorReg.io.datawB := lvdsMst.io.slave_link_num + mirrorReg.io.datawB := io.lvdsMst.slave_link_num mirrorReg.io.enwB := true.B } @@ -325,7 +338,7 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase => tx_start := false.B - when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ + when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){ stateCur := 6.U //statusSync @@ -401,12 +414,12 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase => tx_start := false.B - when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ + when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){ stateCur := 6.U } } .elsewhen( stateCur === 6.U ){ - when( lvdsMst.io.upstream_crc_valid ){ + when( io.lvdsMst.upstream_crc_valid ){ stateCur := 7.U //statusTransmit @@ -487,12 +500,12 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase => tx_start := false.B - when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ + when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){ stateCur := 6.U } } .elsewhen( stateCur === 6.U ){ - when( lvdsMst.io.upstream_crc_valid ){ + when( io.lvdsMst.upstream_crc_valid ){ stateCur := 7.U //statusUnicast @@ -515,14 +528,13 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase => } - trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => - val shiftClosedLoopErr = ShiftRegisters( lvdsMst.io.closed_loop_err, 6, false.B, true.B ) - when( ~shiftClosedLoopErr(0) & lvdsMst.io.closed_loop_err ){ + val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B ) + when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){ - //slvOffLine := lvdsMst.io.link_err_location(5,0) + //slvOffLine := io.lvdsMst.link_err_location(5,0) mirrorReg.io.addrB := 3.U - mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0) + mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0) mirrorReg.io.enwB := true.B } .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){ @@ -558,7 +570,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => - when( lvdsMst.io.upstream_cdr_err ){ + when( io.lvdsMst.upstream_cdr_err ){ // statusCDRErr := true.B mirrorReg.io.addrB := 11.U mirrorReg.io.datawB := 1.U @@ -566,7 +578,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => interrupt := true.B } - when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){ + when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){ // statusCRCErr := true.B mirrorReg.io.addrB := 12.U mirrorReg.io.datawB := 1.U @@ -588,23 +600,23 @@ with BackBoardMstLVDSError{ when( isTransStart | isUnicast ){ addrw := 0.U - } .elsewhen( lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){ + } .elsewhen( io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){ assert( (stateCur === 5.U) || (stateCur === 6.U) ) addrw := addrw + 1.U } when( isTransStart | isUnicast ){ addrr := 0.U - } .elsewhen( lvdsMst.io.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){ + } .elsewhen( io.lvdsMst.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){ addrr := addrr + 1.U } mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast) - lvdsMst.io.tx_data_in := mirrorDown.io.datar + io.lvdsMst.tx_data_in := mirrorDown.io.datar mirrorDown.io.addrr := addrr - mirrorUp.io.enw := lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast) - mirrorUp.io.dataw := lvdsMst.io.rx_data_out + mirrorUp.io.enw := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) + mirrorUp.io.dataw := io.lvdsMst.rx_data_out mirrorUp.io.addrw := addrw } diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index fc5133f..6ae0c7e 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -3,48 +3,34 @@ package BACK import chisel3._ import chisel3.util._ +class LVDS_SLV_Bundle extends Bundle{ + val downstream_rx_data_valid = Input(Bool()) + val downstream_rx_data_out = Input(UInt(8.W)) + val downstream_rx_crc_valid = Input(Bool()) + val downstream_rx_crc_err = Input(Bool()) + val upstream_tx_data_in = Output(UInt(8.W)) + val upstream_tx_data_ready = Input(Bool()) + val downstream_rx_cdr_err = Input(Bool()) + val upstream_rx_cdr_err = Input(Bool()) +} + class BackBoardSlvIO extends Bundle{ - val reset_calib = Input(Bool()) - val oser_pclk = Input(Bool()) - val oser_fclk = Input(Bool()) - val ides_pclk = Input(Bool()) - val ides_fclk = Input(Bool()) - - val lvds_down_din = Input(Bool()) - val lvds_down_dout = Output(Bool()) - val lvds_up_din = Input(Bool()) - val lvds_up_dout = Output(Bool()) - val isOnline = Output(Bool()) val isLast = Input(Bool()) val DCIn = Input(Bool()) + + val lvdsSlv = new LVDS_SLV_Bundle } abstract class BackBoardSlvBase extends Module{ val io: BackBoardSlvIO = IO(new BackBoardSlvIO) - - val lvdsSlv = Module(new Lvds_Bus_Slave) - - lvdsSlv.io.rst_n := ~reset.asBool() - lvdsSlv.io.reset_calib := io.reset_calib - lvdsSlv.io.oser_pclk := io.oser_pclk - lvdsSlv.io.oser_fclk := io.oser_fclk - lvdsSlv.io.ides_pclk := io.ides_pclk - lvdsSlv.io.ides_fclk := io.ides_fclk - - lvdsSlv.io.lvds_down_din := io.lvds_down_din - io.lvds_down_dout := lvdsSlv.io.lvds_down_dout - lvdsSlv.io.lvds_up_din := io.lvds_up_din - io.lvds_up_dout := lvdsSlv.io.lvds_up_dout - val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) - // val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) } @@ -55,39 +41,38 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => val downCnt = Reg(UInt(6.W)) - when( lvdsSlv.io.downstream_rx_data_valid ){ - downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out + when( io.lvdsSlv.downstream_rx_data_valid ){ + downRegTemp(downCnt) := io.lvdsSlv.downstream_rx_data_out downCnt := downCnt + 1.U } .otherwise{ downCnt := 0.U } - val isCrcPass = lvdsSlv.io.downstream_rx_crc_valid & ~lvdsSlv.io.downstream_rx_crc_err + val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err - // when( lvdsSlv.io.downstream_rx_crc_valid ){ - // when( ~lvdsSlv.io.downstream_rx_crc_err ){ + // when( io.lvdsSlv.downstream_rx_crc_valid ){ + // when( ~io.lvdsSlv.downstream_rx_crc_err ){ // for( i <- 1 until 32 ) { // downReg(i) := downRegTemp(i) // } // } // } - // when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){ + // when( RegNext(io.lvdsSlv.downstream_rx_data_valid,false.B) & ~io.lvdsSlv.downstream_rx_data_valid ){ // for( i <- 1 until 32 ) { // downReg(i) := downRegTemp(i) // } // } } - trait BackBoardSlvUp{ this: BackBoardSlvBase => val upCnt = Reg(UInt(6.W)) - lvdsSlv.io.upstream_tx_data_in := upReg(upCnt) + io.lvdsSlv.upstream_tx_data_in := upReg(upCnt) - when( lvdsSlv.io.upstream_tx_data_ready ){ - when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){ + when( io.lvdsSlv.upstream_tx_data_ready ){ + when( ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) ){ upCnt := 0.U } .otherwise{ upCnt := upCnt + 1.U diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index d6632ac..8c52d3b 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -295,9 +295,9 @@ with BackBoardSlvOut16{ when( isCrcPass ){ isDownCDR := false.B isUpCDR := false.B - } .elsewhen( lvdsSlv.io.downstream_rx_cdr_err ){ + } .elsewhen( io.lvdsSlv.downstream_rx_cdr_err ){ isDownCDR := true.B - } .elsewhen( lvdsSlv.io.upstream_rx_cdr_err ){ + } .elsewhen(io. lvdsSlv.upstream_rx_cdr_err ){ isUpCDR := true.B } diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v index 4a80b31..e67dda7 100644 --- a/src/main/verilog/backBoardMstTop.v +++ b/src/main/verilog/backBoardMstTop.v @@ -122,41 +122,106 @@ CLKDIV Inst5_CLKDIVC( .CLKOUT (clk_10m_a) ); +wire frame_info_update_en; +wire [7:0] slave_type_num; +wire [7:0] slave_data_length; +wire tx_start; +wire slave_link_num_valid; +wire [6:0] slave_link_num; +wire downstream_busy; +wire upstream_crc_valid; +wire closed_loop_err; +wire [6:0] link_err_location; +wire upstream_cdr_err; +wire upstream_crc_err; + +wire [7:0] tx_data_in; +wire tx_data_ready; +wire [7:0] rx_data_out; +wire rx_data_valid; + +lvds_bus_master_top i_lvds_bus_master( + .rst_n(rst_n), + .reset_calib(reset_calib), + .oser_pclk(clk_10m_a), + .oser_fclk(clk_50m_a), + .ides_pclk(clk_100m_a), + .ides_fclk(clk_400m_a), + + .lvds_down_dout(lvds_down_dout), + .lvds_up_din(lvds_up_din), + + .frame_info_update_en(frame_info_update_en), + .slave_type_num(slave_type_num), + .slave_data_length(slave_data_length), + + .slave_link_num_valid(slave_link_num_valid), + .slave_link_num(slave_link_num), + + .tx_start(tx_start), + .tx_data_in(tx_data_in), + .tx_data_ready(tx_data_ready), + .downstream_busy(downstream_busy), + .rx_data_out(rx_data_out), + .rx_data_valid(rx_data_valid), + .upstream_crc_valid(upstream_crc_valid), + .upstream_crc_err(upstream_crc_err), + .upstream_crc_err_count(), + .upstream_cdr_err(upstream_cdr_err), + + .closed_loop_err(closed_loop_err), + .link_err_location(link_err_location), + + .test_downstream_tx_en(), + .test_downstream_tx_8b_data(), + .test_downstream_tx_10b_data(), + .test_upstream_rx_busy(), + .test_upstream_rx_10b_data(), + .test_upstream_rx_8b_data() + ); BackBoardMst i_BackBoardMst( - .io_FSMC_ADIn (io_FSMC_ADIn), - .io_FSMC_ADOut(io_FSMC_ADOut), - .io_FSMC_ADOEn(io_FSMC_ADOEn), - .io_FSMC_csn(io_FSMC_csn), - .io_FSMC_rdn(io_FSMC_rdn), - .io_FSMC_wrn(io_FSMC_wrn), - .io_FSMC_advn(io_FSMC_advn), + .io_FSMC_ADIn (io_FSMC_ADIn), + .io_FSMC_ADOut(io_FSMC_ADOut), + .io_FSMC_ADOEn(io_FSMC_ADOEn), + .io_FSMC_csn(io_FSMC_csn), + .io_FSMC_rdn(io_FSMC_rdn), + .io_FSMC_wrn(io_FSMC_wrn), + .io_FSMC_advn(io_FSMC_advn), - // .io_FSMC_ADIn ('d0), - // .io_FSMC_ADOut(), - // .io_FSMC_ADOEn(), - // .io_FSMC_csn(1'b1), - // .io_FSMC_rdn(1'b1), - // .io_FSMC_wrn(1'b1), - // .io_FSMC_advn(1'b1), + .reset(~rst_n), + .clock(clk_10m_a), + .io_oser_pclk(clk_10m_a), + .io_oser_fclk(clk_50m_a), + .io_ides_pclk(clk_100m_a), + .io_ides_fclk(clk_400m_a), - .reset(~rst_n), - .clock(clk_10m_a), - .io_reset_calib(reset_calib), - .io_oser_pclk(clk_10m_a), - .io_oser_fclk(clk_50m_a), - .io_ides_pclk(clk_100m_a), - .io_ides_fclk(clk_400m_a), + .io_interrupt(interrupt), + .io_testIO(testIO), - .io_lvds_down_dout(lvds_down_dout), - .io_lvds_up_din(lvds_up_din), + .io_lvdsMst_frame_info_update_en(frame_info_update_en), + .io_lvdsMst_slave_type_num(slave_type_num), + .io_lvdsMst_slave_data_length(slave_data_length), + .io_lvdsMst_tx_start(tx_start), + .io_lvdsMst_slave_link_num_valid(slave_link_num_valid), + .io_lvdsMst_slave_link_num(slave_link_num), + .io_lvdsMst_downstream_busy(downstream_busy), + .io_lvdsMst_upstream_crc_valid(upstream_crc_valid), + .io_lvdsMst_closed_loop_err(closed_loop_err), + .io_lvdsMst_link_err_location(link_err_location), + + .io_lvdsMst_upstream_cdr_err(upstream_cdr_err), + .io_lvdsMst_upstream_crc_err(upstream_crc_err), + + .io_lvdsMst_tx_data_in(tx_data_in), + .io_lvdsMst_tx_data_ready(tx_data_ready), + .io_lvdsMst_rx_data_out(rx_data_out), + .io_lvdsMst_rx_data_valid(rx_data_valid) - .io_interrupt(interrupt), - .io_testIO(testIO) ); diff --git a/src/main/verilog/backBoardSlvTop.v b/src/main/verilog/backBoardSlvTop.v deleted file mode 100644 index 7add6b9..0000000 --- a/src/main/verilog/backBoardSlvTop.v +++ /dev/null @@ -1,172 +0,0 @@ - - -module slave_top( - - input resetn, - input clock, - - input lvds_up_din_p, - input lvds_up_din_n, - output lvds_up_dout_p, - output lvds_up_dout_n, - - input lvds_down_din_p, - input lvds_down_din_n, - output lvds_down_dout_p, - output lvds_down_dout_n, - - // inout [31:0] digitalIO - output [15:0] digitalIO - -); - -wire clk_400m; -wire clk_400m_a; -wire clk_100m_a; -wire clk_50m_a; -wire clk_10m_a; - -wire lock_o; -wire reset_stop; -wire reset_calib; - -reg rst_n; -reg rstn_d; - -wire [31:0] in; -wire [31:0] out; -wire [31:0] oe; - - - -always@(posedge clk_10m_a) begin - rstn_d <= resetn; - rst_n <= rstn_d; -end - -Gowin_PLLO Gowin_PLLO( - .lock(lock_o), - .clkouta(clk_400m), - .clkin(clock) -); - - - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(lvds_down_dout) -); - - -TLVDS_IBUF lvds_downstream_in( - .O(lvds_down_din), - .I(lvds_down_din_p), - .IB(lvds_down_din_n) -); - - -TLVDS_OBUF lvds_upstream_out( - .O(lvds_up_dout_p), - .OB(lvds_up_dout_n), - .I(lvds_up_dout) -); - - -TLVDS_IBUF lvds_upstream_in( - .O(lvds_up_din), - .I(lvds_up_din_p), - .IB(lvds_up_din_n) -); - - -DHCEN dhcen_inst2 ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - - -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(rst_n), - .pll_lock(lock_o), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_400m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_100m_a) -); - - -defparam Inst2_CLKDIVC.DIV_MODE="2"; -defparam Inst2_CLKDIVC.GSREN="false"; -CLKDIV Inst2_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_100m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_50m_a) -); - - -defparam Inst5_CLKDIVC.DIV_MODE="5"; -defparam Inst5_CLKDIVC.GSREN="false"; -CLKDIV Inst5_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_50m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_10m_a) -); - - - - -// generate -// for( genvar i = 0; i < 32; i = i + 1 ) begin -// IOBUF uut( -// .O(in[i]), -// .IO(digitalIO[i]), -// .I(out[i]), -// .OEN(~oe[i]) -// ); -// end -// endgenerate - -assign digitalIO = out[15:0]; -assign in = 32'hAA55AA55; - -BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO( - .reset(~rst_n), - .clock(clk_10m_a), - .io_reset_calib(reset_calib), - .io_oser_pclk(clk_10m_a), - .io_oser_fclk(clk_50m_a), - .io_ides_pclk(clk_100m_a), - .io_ides_fclk(clk_400m_a), - - .io_lvds_down_din(lvds_down_din), - .io_lvds_down_dout(lvds_down_dout), - .io_lvds_up_din(lvds_up_din), - .io_lvds_up_dout(lvds_up_dout), - - .in(in), - .out(out), - .oe(oe) -); - - -endmodule - - - - diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v index 3e9887c..c74d5ee 100644 --- a/src/main/verilog/di16_top.v +++ b/src/main/verilog/di16_top.v @@ -2,7 +2,8 @@ module di16_top( - input clock, + input clock, + input resetn, input lvds_up_din_p, input lvds_up_din_n, @@ -16,14 +17,13 @@ module di16_top( output isOnline, input isLast, - input DCIn, output LED_PR, input [15:0] in ); -wire resetn = 1'b1; +wire DCIn = 1'b0; wire clk_400m; wire clk_400m_a; @@ -130,19 +130,63 @@ CLKDIV Inst5_CLKDIVC( .CLKOUT (clk_10m_a) ); +wire [7:0] downstream_rx_data_out; +wire downstream_rx_data_valid; +wire downstream_rx_crc_valid; +wire downstream_rx_crc_err; +wire upstream_tx_data_ready; +wire [7:0] upstream_tx_data_in; + +wire downstream_rx_cdr_err; +wire upstream_rx_cdr_err; + +lvds_bus_slave_top i_lvds_bus_slave( + .rst_n(rst_n), + .reset_calib(reset_calib), + .oser_pclk(clk_10m_a), + .oser_fclk(clk_50m_a), + .ides_pclk(clk_100m_a), + .ides_fclk(clk_400m_a), + + .lvds_down_din(lvds_down_din), + .lvds_down_dout(lvds_down_dout), + .lvds_up_din(lvds_up_din), + .lvds_up_dout(lvds_up_dout), + + .downstream_rx_data_valid(downstream_rx_data_valid), + .downstream_rx_unicast_pkg_valid(), + .downstream_rx_data_out(downstream_rx_data_out), + .downstream_rx_crc_valid(downstream_rx_crc_valid), + .downstream_rx_crc_err(downstream_rx_crc_err), + .downstream_rx_crc_err_counter(), + .downstream_rx_cdr_err(downstream_rx_cdr_err), + .downstream_sync(), + .upstream_tx_data_ready(upstream_tx_data_ready), + .upstream_tx_unicast_pkg_ready(), + .upstream_tx_data_in(upstream_tx_data_in), + .upstream_rx_crc_valid(), + .upstream_rx_crc_err(), + .upstream_rx_crc_err_counter(), + .upstream_rx_cdr_err(upstream_rx_cdr_err), + + .local_slave_id(), + .test_downstream_rx_10b_data(), + .test_downstream_rx_8b_data(), + .test_downstream_rx_state_machine(), + .test_downstream_tx_en(), + .test_downstream_tx_8b_data(), + .test_downstream_tx_10b_data(), + .test_upstream_rx_10b_data(), + .test_upstream_rx_8b_data(), + .test_upstream_rx_state_machine(), + .test_upstream_tx_en(), + .test_upstream_tx_8b_data(), + .test_upstream_tx_10b_data() + ); + DIn16 i_din16( .reset(~rst_n), .clock(clk_10m_a), - .io_reset_calib(reset_calib), - .io_oser_pclk(clk_10m_a), - .io_oser_fclk(clk_50m_a), - .io_ides_pclk(clk_100m_a), - .io_ides_fclk(clk_400m_a), - - .io_lvds_down_din(lvds_down_din), - .io_lvds_down_dout(lvds_down_dout), - .io_lvds_up_din(lvds_up_din), - .io_lvds_up_dout(lvds_up_dout), .io_isOnline(isOnline), .io_isLast(isLast), @@ -152,10 +196,18 @@ DIn16 i_din16( .param_moduleID(`MODULEID), .param_hwVersion(`HWVERSION), .param_swVersion(`SWVERSION), - // .param_batchID(`BATCHID), .param_serial(`SERIAL), .LED_PR(LED_PR), - .in(in) + .in(in), + + .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), + .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), + .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid), + .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err), + .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready), + .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in), + .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), + .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err) ); endmodule diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v index dabf37d..5a2beee 100644 --- a/src/main/verilog/do16_top.v +++ b/src/main/verilog/do16_top.v @@ -2,8 +2,8 @@ module do16_top( - - input clock, + input clock, + input resetn, input lvds_up_din_p, input lvds_up_din_n, @@ -17,7 +17,7 @@ module do16_top( output isOnline, input isLast, - input DCIn, + output LED_PR, output [15:0] out, @@ -26,7 +26,7 @@ module do16_top( ); -wire resetn = 1'b1; +wire DCIn = 1'b0; wire clk_400m; wire clk_400m_a; @@ -134,19 +134,64 @@ CLKDIV Inst5_CLKDIVC( .CLKOUT (clk_10m_a) ); +wire [7:0] downstream_rx_data_out; +wire downstream_rx_data_valid; +wire downstream_rx_crc_valid; +wire downstream_rx_crc_err; +wire upstream_tx_data_ready; +wire [7:0] upstream_tx_data_in; + +wire downstream_rx_cdr_err; +wire upstream_rx_cdr_err; + +lvds_bus_slave_top i_lvds_bus_slave( + .rst_n(rst_n), + .reset_calib(reset_calib), + .oser_pclk(clk_10m_a), + .oser_fclk(clk_50m_a), + .ides_pclk(clk_100m_a), + .ides_fclk(clk_400m_a), + + .lvds_down_din(lvds_down_din), + .lvds_down_dout(lvds_down_dout), + .lvds_up_din(lvds_up_din), + .lvds_up_dout(lvds_up_dout), + + .downstream_rx_data_valid(downstream_rx_data_valid), + .downstream_rx_unicast_pkg_valid(), + .downstream_rx_data_out(downstream_rx_data_out), + .downstream_rx_crc_valid(downstream_rx_crc_valid), + .downstream_rx_crc_err(downstream_rx_crc_err), + .downstream_rx_crc_err_counter(), + .downstream_rx_cdr_err(downstream_rx_cdr_err), + .downstream_sync(), + .upstream_tx_data_ready(upstream_tx_data_ready), + .upstream_tx_unicast_pkg_ready(), + .upstream_tx_data_in(upstream_tx_data_in), + .upstream_rx_crc_valid(), + .upstream_rx_crc_err(), + .upstream_rx_crc_err_counter(), + .upstream_rx_cdr_err(upstream_rx_cdr_err), + + .local_slave_id(), + .test_downstream_rx_10b_data(), + .test_downstream_rx_8b_data(), + .test_downstream_rx_state_machine(), + .test_downstream_tx_en(), + .test_downstream_tx_8b_data(), + .test_downstream_tx_10b_data(), + .test_upstream_rx_10b_data(), + .test_upstream_rx_8b_data(), + .test_upstream_rx_state_machine(), + .test_upstream_tx_en(), + .test_upstream_tx_8b_data(), + .test_upstream_tx_10b_data() + ); + + DOut16 i_dout16( .reset(~rst_n), .clock(clk_10m_a), - .io_reset_calib(reset_calib), - .io_oser_pclk(clk_10m_a), - .io_oser_fclk(clk_50m_a), - .io_ides_pclk(clk_100m_a), - .io_ides_fclk(clk_400m_a), - - .io_lvds_down_din(lvds_down_din), - .io_lvds_down_dout(lvds_down_dout), - .io_lvds_up_din(lvds_up_din), - .io_lvds_up_dout(lvds_up_dout), .io_isOnline(isOnline), .io_isLast(isLast), @@ -161,7 +206,16 @@ DOut16 i_dout16( .LED_PR(LED_PR), .out(out), .flt_0(flt_0), - .flt_1(flt_1) + .flt_1(flt_1), + + .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), + .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), + .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid), + .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err), + .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready), + .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in), + .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), + .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err) ); endmodule