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ebus拉到顶层

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This commit is contained in:
RuigeLee
2024-05-16 20:02:03 +08:00
parent 45e46b2d46
commit aaf932ffd4
8 changed files with 300 additions and 305 deletions
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59
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -3,48 +3,34 @@ package BACK
import chisel3._
import chisel3.util._
class LVDS_SLV_Bundle extends Bundle{
val downstream_rx_data_valid = Input(Bool())
val downstream_rx_data_out = Input(UInt(8.W))
val downstream_rx_crc_valid = Input(Bool())
val downstream_rx_crc_err = Input(Bool())
val upstream_tx_data_in = Output(UInt(8.W))
val upstream_tx_data_ready = Input(Bool())
val downstream_rx_cdr_err = Input(Bool())
val upstream_rx_cdr_err = Input(Bool())
}
class BackBoardSlvIO extends Bundle{
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val lvds_down_din = Input(Bool())
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val lvds_up_dout = Output(Bool())
val isOnline = Output(Bool())
val isLast = Input(Bool())
val DCIn = Input(Bool())
val lvdsSlv = new LVDS_SLV_Bundle
}
abstract class BackBoardSlvBase extends Module{
val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
val lvdsSlv = Module(new Lvds_Bus_Slave)
lvdsSlv.io.rst_n := ~reset.asBool()
lvdsSlv.io.reset_calib := io.reset_calib
lvdsSlv.io.oser_pclk := io.oser_pclk
lvdsSlv.io.oser_fclk := io.oser_fclk
lvdsSlv.io.ides_pclk := io.ides_pclk
lvdsSlv.io.ides_fclk := io.ides_fclk
lvdsSlv.io.lvds_down_din := io.lvds_down_din
io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
// val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
}
@@ -55,39 +41,38 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
val downCnt = Reg(UInt(6.W))
when( lvdsSlv.io.downstream_rx_data_valid ){
downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
when( io.lvdsSlv.downstream_rx_data_valid ){
downRegTemp(downCnt) := io.lvdsSlv.downstream_rx_data_out
downCnt := downCnt + 1.U
} .otherwise{
downCnt := 0.U
}
val isCrcPass = lvdsSlv.io.downstream_rx_crc_valid & ~lvdsSlv.io.downstream_rx_crc_err
val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
// when( lvdsSlv.io.downstream_rx_crc_valid ){
// when( ~lvdsSlv.io.downstream_rx_crc_err ){
// when( io.lvdsSlv.downstream_rx_crc_valid ){
// when( ~io.lvdsSlv.downstream_rx_crc_err ){
// for( i <- 1 until 32 ) {
// downReg(i) := downRegTemp(i)
// }
// }
// }
// when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){
// when( RegNext(io.lvdsSlv.downstream_rx_data_valid,false.B) & ~io.lvdsSlv.downstream_rx_data_valid ){
// for( i <- 1 until 32 ) {
// downReg(i) := downRegTemp(i)
// }
// }
}
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
val upCnt = Reg(UInt(6.W))
lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
io.lvdsSlv.upstream_tx_data_in := upReg(upCnt)
when( lvdsSlv.io.upstream_tx_data_ready ){
when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){
when( io.lvdsSlv.upstream_tx_data_ready ){
when( ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) ){
upCnt := 0.U
} .otherwise{
upCnt := upCnt + 1.U