ebus拉到顶层
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RuigeLee
@@ -17,29 +17,52 @@ class FSMC_Port_Bundle extends Bundle{
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val advn = Input(Bool())
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}
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class LVDS_MST_Bundle extends Bundle{
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val frame_info_update_en = Output(Bool())
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val slave_type_num = Output(UInt(8.W))
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val slave_data_length = Output(UInt(8.W))
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val tx_start = Output(Bool())
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val slave_link_num_valid = Input(Bool())
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val slave_link_num = Input(UInt(7.W))
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val downstream_busy = Input(Bool())
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val upstream_crc_valid = Input(Bool())
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val closed_loop_err = Input(Bool())
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val link_err_location = Input(UInt(7.W))
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val upstream_cdr_err = Input(Bool())
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val upstream_crc_err = Input(Bool())
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val tx_data_ready = Input(Bool())
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val tx_data_in = Output(UInt(8.W))
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val rx_data_valid = Input(Bool())
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val rx_data_out = Input(UInt(8.W))
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}
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class BackBoardMstIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool()) //10M
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val oser_fclk = Input(Bool()) //50M
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val ides_pclk = Input(Bool()) //100M
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val ides_pclk = Input(Bool()) //100M
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val ides_fclk = Input(Bool()) //400M
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val interrupt = Output(Bool())
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val testIO = Input(Bool())
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val lvdsMst = new LVDS_MST_Bundle
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}
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class BackBoardMstBase extends Module{ //10M
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val io: BackBoardMstIO = IO(new BackBoardMstIO)
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val lvdsMst = Module(new Lvds_Bus_Master)
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val mirrorDown = Module(new MirrorSRAMDown())
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val mirrorUp = Module(new MirrorSRAMUp())
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val mirrorReg = Module(new MirrorSRAMDP())
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@@ -61,16 +84,6 @@ class BackBoardMstBase extends Module{ //10M
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val interrupt = RegInit(false.B); io.interrupt := interrupt
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val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1
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lvdsMst.io.rst_n := ~reset.asBool
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lvdsMst.io.reset_calib := io.reset_calib
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lvdsMst.io.oser_pclk := io.oser_pclk
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lvdsMst.io.oser_fclk := io.oser_fclk
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lvdsMst.io.ides_pclk := io.ides_pclk
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lvdsMst.io.ides_fclk := io.ides_fclk
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io.lvds_down_dout := lvdsMst.io.lvds_down_dout
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lvdsMst.io.lvds_up_din := io.lvds_up_din
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@@ -160,10 +173,10 @@ with BackBoardMstFSMC
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val tx_start = RegInit(false.B)
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lvdsMst.io.frame_info_update_en := frame_info_update_en
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lvdsMst.io.slave_type_num := slave_type_num
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lvdsMst.io.slave_data_length := slaveDataLength
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lvdsMst.io.tx_start := tx_start
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io.lvdsMst.frame_info_update_en := frame_info_update_en
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io.lvdsMst.slave_type_num := slave_type_num
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io.lvdsMst.slave_data_length := slaveDataLength
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io.lvdsMst.tx_start := tx_start
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val stateCur = RegInit(15.U(4.W))
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@@ -231,12 +244,12 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
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tx_start := false.B
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timeoutCnt := timeoutCnt + 1.U
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when( lvdsMst.io.slave_link_num_valid ){
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when( io.lvdsMst.slave_link_num_valid ){
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stateCur := 6.U
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//linkNum
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mirrorReg.io.addrB := 5.U
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mirrorReg.io.datawB := lvdsMst.io.slave_link_num
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mirrorReg.io.datawB := io.lvdsMst.slave_link_num
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mirrorReg.io.enwB := true.B
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}
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@@ -325,7 +338,7 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
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stateCur := 6.U
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//statusSync
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@@ -401,12 +414,12 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
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stateCur := 6.U
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}
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} .elsewhen( stateCur === 6.U ){
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when( lvdsMst.io.upstream_crc_valid ){
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when( io.lvdsMst.upstream_crc_valid ){
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stateCur := 7.U
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//statusTransmit
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@@ -487,12 +500,12 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
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stateCur := 6.U
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}
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} .elsewhen( stateCur === 6.U ){
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when( lvdsMst.io.upstream_crc_valid ){
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when( io.lvdsMst.upstream_crc_valid ){
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stateCur := 7.U
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//statusUnicast
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@@ -515,14 +528,13 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
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}
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trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
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val shiftClosedLoopErr = ShiftRegisters( lvdsMst.io.closed_loop_err, 6, false.B, true.B )
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when( ~shiftClosedLoopErr(0) & lvdsMst.io.closed_loop_err ){
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val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B )
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when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){
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//slvOffLine := lvdsMst.io.link_err_location(5,0)
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//slvOffLine := io.lvdsMst.link_err_location(5,0)
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mirrorReg.io.addrB := 3.U
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mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
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mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0)
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mirrorReg.io.enwB := true.B
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} .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
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@@ -558,7 +570,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
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when( lvdsMst.io.upstream_cdr_err ){
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when( io.lvdsMst.upstream_cdr_err ){
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// statusCDRErr := true.B
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mirrorReg.io.addrB := 11.U
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mirrorReg.io.datawB := 1.U
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@@ -566,7 +578,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
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interrupt := true.B
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}
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when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
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when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
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// statusCRCErr := true.B
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mirrorReg.io.addrB := 12.U
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mirrorReg.io.datawB := 1.U
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@@ -588,23 +600,23 @@ with BackBoardMstLVDSError{
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when( isTransStart | isUnicast ){
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addrw := 0.U
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} .elsewhen( lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
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} .elsewhen( io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
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assert( (stateCur === 5.U) || (stateCur === 6.U) )
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addrw := addrw + 1.U
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}
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when( isTransStart | isUnicast ){
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addrr := 0.U
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} .elsewhen( lvdsMst.io.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
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} .elsewhen( io.lvdsMst.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
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addrr := addrr + 1.U
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}
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mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
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lvdsMst.io.tx_data_in := mirrorDown.io.datar
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io.lvdsMst.tx_data_in := mirrorDown.io.datar
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mirrorDown.io.addrr := addrr
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mirrorUp.io.enw := lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast)
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mirrorUp.io.dataw := lvdsMst.io.rx_data_out
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mirrorUp.io.enw := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast)
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mirrorUp.io.dataw := io.lvdsMst.rx_data_out
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mirrorUp.io.addrw := addrw
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}
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