ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ebus拉到顶层

Browse Source
This commit is contained in:
RuigeLee
2024-05-16 20:02:03 +08:00
parent 45e46b2d46
commit aaf932ffd4
8 changed files with 300 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -17,29 +17,52 @@ class FSMC_Port_Bundle extends Bundle{
val advn = Input(Bool())
}
class LVDS_MST_Bundle extends Bundle{
val frame_info_update_en = Output(Bool())
val slave_type_num = Output(UInt(8.W))
val slave_data_length = Output(UInt(8.W))
val tx_start = Output(Bool())
val slave_link_num_valid = Input(Bool())
val slave_link_num = Input(UInt(7.W))
val downstream_busy = Input(Bool())
val upstream_crc_valid = Input(Bool())
val closed_loop_err = Input(Bool())
val link_err_location = Input(UInt(7.W))
val upstream_cdr_err = Input(Bool())
val upstream_crc_err = Input(Bool())
val tx_data_ready = Input(Bool())
val tx_data_in = Output(UInt(8.W))
val rx_data_valid = Input(Bool())
val rx_data_out = Input(UInt(8.W))
}
class BackBoardMstIO extends Bundle{
val FSMC = new FSMC_Port_Bundle
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool()) //10M
val oser_fclk = Input(Bool()) //50M
val ides_pclk = Input(Bool()) //100M
val ides_pclk = Input(Bool()) //100M
val ides_fclk = Input(Bool()) //400M
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val interrupt = Output(Bool())
val testIO = Input(Bool())
val lvdsMst = new LVDS_MST_Bundle
}
class BackBoardMstBase extends Module{ //10M
val io: BackBoardMstIO = IO(new BackBoardMstIO)
val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAMDown())
val mirrorUp = Module(new MirrorSRAMUp())
val mirrorReg = Module(new MirrorSRAMDP())
@@ -61,16 +84,6 @@ class BackBoardMstBase extends Module{ //10M
val interrupt = RegInit(false.B); io.interrupt := interrupt
val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1
lvdsMst.io.rst_n := ~reset.asBool
lvdsMst.io.reset_calib := io.reset_calib
lvdsMst.io.oser_pclk := io.oser_pclk
lvdsMst.io.oser_fclk := io.oser_fclk
lvdsMst.io.ides_pclk := io.ides_pclk
lvdsMst.io.ides_fclk := io.ides_fclk
io.lvds_down_dout := lvdsMst.io.lvds_down_dout
lvdsMst.io.lvds_up_din := io.lvds_up_din
@@ -160,10 +173,10 @@ with BackBoardMstFSMC
val tx_start = RegInit(false.B)
lvdsMst.io.frame_info_update_en := frame_info_update_en
lvdsMst.io.slave_type_num := slave_type_num
lvdsMst.io.slave_data_length := slaveDataLength
lvdsMst.io.tx_start := tx_start
io.lvdsMst.frame_info_update_en := frame_info_update_en
io.lvdsMst.slave_type_num := slave_type_num
io.lvdsMst.slave_data_length := slaveDataLength
io.lvdsMst.tx_start := tx_start
val stateCur = RegInit(15.U(4.W))
@@ -231,12 +244,12 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
tx_start := false.B
timeoutCnt := timeoutCnt + 1.U
when( lvdsMst.io.slave_link_num_valid ){
when( io.lvdsMst.slave_link_num_valid ){
stateCur := 6.U
//linkNum
mirrorReg.io.addrB := 5.U
mirrorReg.io.datawB := lvdsMst.io.slave_link_num
mirrorReg.io.datawB := io.lvdsMst.slave_link_num
mirrorReg.io.enwB := true.B
}
@@ -325,7 +338,7 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
stateCur := 6.U
//statusSync
@@ -401,12 +414,12 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
stateCur := 6.U
}
} .elsewhen( stateCur === 6.U ){
when( lvdsMst.io.upstream_crc_valid ){
when( io.lvdsMst.upstream_crc_valid ){
stateCur := 7.U
//statusTransmit
@@ -487,12 +500,12 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
stateCur := 6.U
}
} .elsewhen( stateCur === 6.U ){
when( lvdsMst.io.upstream_crc_valid ){
when( io.lvdsMst.upstream_crc_valid ){
stateCur := 7.U
//statusUnicast
@@ -515,14 +528,13 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
}
trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
val shiftClosedLoopErr = ShiftRegisters( lvdsMst.io.closed_loop_err, 6, false.B, true.B )
when( ~shiftClosedLoopErr(0) & lvdsMst.io.closed_loop_err ){
val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B )
when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){
//slvOffLine := lvdsMst.io.link_err_location(5,0)
//slvOffLine := io.lvdsMst.link_err_location(5,0)
mirrorReg.io.addrB := 3.U
mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0)
mirrorReg.io.enwB := true.B
} .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
@@ -558,7 +570,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.upstream_cdr_err ){
when( io.lvdsMst.upstream_cdr_err ){
// statusCDRErr := true.B
mirrorReg.io.addrB := 11.U
mirrorReg.io.datawB := 1.U
@@ -566,7 +578,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
interrupt := true.B
}
when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
// statusCRCErr := true.B
mirrorReg.io.addrB := 12.U
mirrorReg.io.datawB := 1.U
@@ -588,23 +600,23 @@ with BackBoardMstLVDSError{
when( isTransStart | isUnicast ){
addrw := 0.U
} .elsewhen( lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
} .elsewhen( io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
assert( (stateCur === 5.U) || (stateCur === 6.U) )
addrw := addrw + 1.U
}
when( isTransStart | isUnicast ){
addrr := 0.U
} .elsewhen( lvdsMst.io.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
} .elsewhen( io.lvdsMst.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
addrr := addrr + 1.U
}
mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
lvdsMst.io.tx_data_in := mirrorDown.io.datar
io.lvdsMst.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr
mirrorUp.io.enw := lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast)
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.enw := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast)
mirrorUp.io.dataw := io.lvdsMst.rx_data_out
mirrorUp.io.addrw := addrw
}

59
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -3,48 +3,34 @@ package BACK
import chisel3._
import chisel3.util._
class LVDS_SLV_Bundle extends Bundle{
val downstream_rx_data_valid = Input(Bool())
val downstream_rx_data_out = Input(UInt(8.W))
val downstream_rx_crc_valid = Input(Bool())
val downstream_rx_crc_err = Input(Bool())
val upstream_tx_data_in = Output(UInt(8.W))
val upstream_tx_data_ready = Input(Bool())
val downstream_rx_cdr_err = Input(Bool())
val upstream_rx_cdr_err = Input(Bool())
}
class BackBoardSlvIO extends Bundle{
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val lvds_down_din = Input(Bool())
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val lvds_up_dout = Output(Bool())
val isOnline = Output(Bool())
val isLast = Input(Bool())
val DCIn = Input(Bool())
val lvdsSlv = new LVDS_SLV_Bundle
}
abstract class BackBoardSlvBase extends Module{
val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
val lvdsSlv = Module(new Lvds_Bus_Slave)
lvdsSlv.io.rst_n := ~reset.asBool()
lvdsSlv.io.reset_calib := io.reset_calib
lvdsSlv.io.oser_pclk := io.oser_pclk
lvdsSlv.io.oser_fclk := io.oser_fclk
lvdsSlv.io.ides_pclk := io.ides_pclk
lvdsSlv.io.ides_fclk := io.ides_fclk
lvdsSlv.io.lvds_down_din := io.lvds_down_din
io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
// val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
}
@@ -55,39 +41,38 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
val downCnt = Reg(UInt(6.W))
when( lvdsSlv.io.downstream_rx_data_valid ){
downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
when( io.lvdsSlv.downstream_rx_data_valid ){
downRegTemp(downCnt) := io.lvdsSlv.downstream_rx_data_out
downCnt := downCnt + 1.U
} .otherwise{
downCnt := 0.U
}
val isCrcPass = lvdsSlv.io.downstream_rx_crc_valid & ~lvdsSlv.io.downstream_rx_crc_err
val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
// when( lvdsSlv.io.downstream_rx_crc_valid ){
// when( ~lvdsSlv.io.downstream_rx_crc_err ){
// when( io.lvdsSlv.downstream_rx_crc_valid ){
// when( ~io.lvdsSlv.downstream_rx_crc_err ){
// for( i <- 1 until 32 ) {
// downReg(i) := downRegTemp(i)
// }
// }
// }
// when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){
// when( RegNext(io.lvdsSlv.downstream_rx_data_valid,false.B) & ~io.lvdsSlv.downstream_rx_data_valid ){
// for( i <- 1 until 32 ) {
// downReg(i) := downRegTemp(i)
// }
// }
}
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
val upCnt = Reg(UInt(6.W))
lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
io.lvdsSlv.upstream_tx_data_in := upReg(upCnt)
when( lvdsSlv.io.upstream_tx_data_ready ){
when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){
when( io.lvdsSlv.upstream_tx_data_ready ){
when( ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) ){
upCnt := 0.U
} .otherwise{
upCnt := upCnt + 1.U

4
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -295,9 +295,9 @@ with BackBoardSlvOut16{
when( isCrcPass ){
isDownCDR := false.B
isUpCDR := false.B
} .elsewhen( lvdsSlv.io.downstream_rx_cdr_err ){
} .elsewhen( io.lvdsSlv.downstream_rx_cdr_err ){
isDownCDR := true.B
} .elsewhen( lvdsSlv.io.upstream_rx_cdr_err ){
} .elsewhen(io. lvdsSlv.upstream_rx_cdr_err ){
isUpCDR := true.B
}