ebus拉到顶层

Makefile

@@ -15,7 +15,6 @@ back:
 	rm -f ./generated/*
 	sbt "test:runMain test.testModule"
 	cp ./src/main/verilog/backBoardMstTop.v ./generated/
-	# cp ./src/main/verilog/backBoardSlvTop.v ./generated/
 	cp ./src/main/verilog/oser_rst.v ./generated/
 	cp ./src/main/verilog/di16_top.v ./generated/
 	cp ./src/main/verilog/do16_top.v ./generated/