修正了DIn16的风格

src/main/scala/backBoard/LocalRegisters.scala

@@ -102,15 +102,16 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
 
 
 
-trait BackBoardSlvIn { this: BackBoardSlvLocal =>
+trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
 
-  def gp: Int
+  val inPin = Wire(UInt(16.W))
 
 
-  val in = IO(Input(UInt((8*gp).W)))
-
   val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(3.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
   val flitTrigger = Wire(Vec(9, Bool()))
+  val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
+  val digitalIn     = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
+
 
   flitTrigger(0) := ~RegNext(flitTrigger(0))
 
@@ -154,30 +155,19 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
     flitCnt(8) := ~flitCnt(8)
   }
 
-  for( j <- 0 until gp ) {
 
-    val digitalFilter = RegInit( 1.U(8.W) )
 
-    when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
-      digitalFilter := downRegTemp(4+j)
-    }
 
-    val digitalIn = Reg( Vec(8, Bool()) )
-
-    when( statusPage === 0.U ){
-      upReg(2+j) := Cat( digitalIn.reverse  )
-      upReg(4+j) := digitalFilter
-    }
 
 
   for( i <- 0 until 8 ) {
-
+    for( j <- 0 until 2 ) {
       val flitter = RegInit(VecInit( Seq.fill(32){false.B}))
       val flitHi  = RegInit(0.U((log2Ceil(32)).W))
-      val shiftIn = RegNext( in(i+8*j) )
+      val shiftIn = RegNext( inPin(i+8*j) )
 
       ( 0 until 9 ).map{ k => 
-        when( digitalFilter === k.U ){
+        when( digitalFilter(j) === k.U ){
           when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
             flitter(0) := shiftIn
             (1 until 32).map{ k =>
@@ -193,9 +183,9 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
             }
 
             when( flitHi >= 25.U ){
-              digitalIn(i) := true.B
+              digitalIn(j)(i) := true.B
             } .elsewhen( flitHi <= 6.U ){
-              digitalIn(i) := false.B
+              digitalIn(j)(i) := false.B
             }      
 
             // val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) )
@@ -216,9 +206,26 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
 
 class DIn16 extends BackBoardSlvLocal
 with BackBoardSlvStatusPR
-with BackBoardSlvIn{
+with BackBoardSlvIn16{
-  def gp = 2
   
+  val in = IO(Input(UInt(16.W)))
+
+  inPin := in
+
+
+
+
+  when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
+    digitalFilter(0) := downRegTemp(4)
+    digitalFilter(1) := downRegTemp(5)
+  }
+
+  when( statusPage === 0.U ){
+    upReg(2) := Cat( digitalIn(0).reverse  )
+    upReg(3) := Cat( digitalIn(1).reverse  )
+    upReg(4) := digitalFilter(0)
+    upReg(5) := digitalFilter(1)
+  }
 }
 
 
@@ -260,21 +267,11 @@ with BackBoardSlvOut16{
     upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
   }
 
+  chsWire := 0.U.asTypeOf(chsWire)
+  out := outPin
+
 
 }
 
-// class BackBoardSlvOut16 extends BackBoardSlvLocal{
-//   val in  = IO(Input(UInt(32.W)))
-//   val out = IO(Output(UInt(32.W)))
-//   val oe  = IO(Output(UInt(32.W)))
 
 
-
-//   out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
-//   oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
-
-//   for( i <- 0 until 4 ) {
-//     upReg(i) := in( i*8+7,8*i )
-//   }
-// }
-

src/test/scala/gcd/test.scala

@@ -24,6 +24,10 @@ object testModule extends App {
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new DIn16 })
     ))
+
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new DOut16 })
+    ))
   // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
   //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
   //   ))