278 lines
6.4 KiB
Scala
278 lines
6.4 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class ManualParamBundle extends Bundle{
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val vendorID = UInt( 16.W )
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val moduleID = UInt( 16.W )
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val hwVersion = UInt( 16.W )
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val swVersion = UInt( 16.W )
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val batchID = UInt( 16.W )
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val serial = UInt( 48.W )
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}
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abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
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val param = IO(Input( new ManualParamBundle ))
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val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass )
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val statusP = RegInit(false.B)
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val statusRF = RegInit(false.B)
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val statusPR = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass )
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val statusER = RegInit(false.B)
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val statusLE = RegInit(false.B)
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upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
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upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) )
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when( statusPage === 15.U ){
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upReg(2) := 0.U
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upReg(3) := 0.U
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upReg(4) := 0.U
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upReg(5) := 0.U
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upReg(16) := param.vendorID(7,0)
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upReg(17) := param.vendorID(15,8)
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upReg(18) := param.moduleID(7,0)
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upReg(19) := param.moduleID(15,8)
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upReg(20) := param.hwVersion(7,0)
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upReg(21) := param.hwVersion(15,8)
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upReg(22) := param.swVersion(7,0)
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upReg(23) := param.swVersion(15,8)
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upReg(24) := param.batchID(7,0)
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upReg(25) := param.batchID(15,8)
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upReg(26) := param.serial(7,0)
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upReg(27) := param.serial(15,8)
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upReg(28) := param.serial(23,16)
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upReg(29) := param.serial(31,24)
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upReg(30) := param.serial(39,32)
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upReg(31) := param.serial(47,40)
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}
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val (usCounter, usTrigger) = Counter(Range(0, 10))
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}
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trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
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val flashCounter = RegInit( 0.U( 19.W ) )
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val flash2HZ = Reg(Bool())
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val flash1HZ = Reg(Bool())
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when( usTrigger ){
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when( flashCounter >= 500000.U ){
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flashCounter := 0.U
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flash2HZ := ~flash2HZ
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when( flash2HZ ){
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flash1HZ := ~flash1HZ
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}
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} .otherwise{
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flashCounter := flashCounter + 1.U
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}
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}
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val LED_PR = IO(Output( Bool() ))
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LED_PR := ~Mux1H(Seq(
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( statusPR === "b00".U ) -> flash2HZ,
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( statusPR === "b01".U ) -> flash1HZ,
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( statusPR === "b10".U ) -> true.B,
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( statusPR === "b11".U ) -> false.B,
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))
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}
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trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
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val inPin = Wire(UInt(16.W))
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val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(3.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
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val flitTrigger = Wire(Vec(9, Bool()))
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val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
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val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
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flitTrigger(0) := ~RegNext(flitTrigger(0))
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flitTrigger(1) := flitCnt(1) === 7.U
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when( ~RegNext(usTrigger) & usTrigger ){
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flitCnt(1) := flitCnt(1) + 1.U
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}
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flitTrigger(2) := flitCnt(2)
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when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
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flitCnt(2) := ~flitCnt(2)
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}
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flitTrigger(3) := flitCnt(3)
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when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
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flitCnt(3) := ~flitCnt(3)
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}
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flitTrigger(4) := flitCnt(4)
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when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
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flitCnt(4) := ~flitCnt(4)
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}
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flitTrigger(5) := flitCnt(5)
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when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
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flitCnt(5) := ~flitCnt(5)
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}
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flitTrigger(6) := flitCnt(6)
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when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
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flitCnt(6) := ~flitCnt(6)
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}
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flitTrigger(7) := flitCnt(7)
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when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
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flitCnt(7) := ~flitCnt(7)
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}
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flitTrigger(8) := flitCnt(8)
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when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
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flitCnt(8) := ~flitCnt(8)
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}
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for( i <- 0 until 8 ) {
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for( j <- 0 until 2 ) {
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val flitter = RegInit(VecInit( Seq.fill(32){false.B}))
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val flitHi = RegInit(0.U((log2Ceil(32)).W))
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val shiftIn = RegNext( inPin(i+8*j) )
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( 0 until 9 ).map{ k =>
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when( digitalFilter(j) === k.U ){
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when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
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flitter(0) := shiftIn
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(1 until 32).map{ k =>
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flitter(k) := flitter(k-1)
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}
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when( (~flitter(31) & ~flitter(0)) | (flitter(31) & flitter(0)) ){
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flitHi := flitHi
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} .elsewhen( ~flitter(31) & flitter(0) ){
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flitHi := flitHi + 1.U
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} .elsewhen( flitter(31) & ~flitter(0) ){
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flitHi := flitHi - 1.U
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}
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when( flitHi >= 25.U ){
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digitalIn(j)(i) := true.B
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} .elsewhen( flitHi <= 6.U ){
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digitalIn(j)(i) := false.B
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}
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// val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) )
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// assert( flitHi <= 31.U )
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// assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
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}
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}
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}
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}
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}
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}
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class DIn16 extends BackBoardSlvLocal
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with BackBoardSlvStatusPR
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with BackBoardSlvIn16{
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val in = IO(Input(UInt(16.W)))
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inPin := in
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when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
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digitalFilter(0) := downRegTemp(4)
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digitalFilter(1) := downRegTemp(5)
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}
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when( statusPage === 0.U ){
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upReg(2) := Cat( digitalIn(0).reverse )
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upReg(3) := Cat( digitalIn(1).reverse )
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upReg(4) := digitalFilter(0)
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upReg(5) := digitalFilter(1)
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}
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}
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trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
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val outReg = RegInit(0.U(16.W))
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val chsWire = Wire( Vec(16, UInt(2.W)) )
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val mthodReg = RegInit(0.U(16.W))
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val valueReg = RegInit(0.U(16.W))
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val outPin = Wire(UInt(16.W))
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outPin :=
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Mux(statusPR === 3.U, outReg, (mthodReg & valueReg) | (~mthodReg & outReg))
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}
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class DOut16 extends BackBoardSlvLocal
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with BackBoardSlvStatusPR
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with BackBoardSlvOut16{
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val out = IO(Output(UInt(16.W)))
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when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
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outReg := Cat(downRegTemp(3), downRegTemp(2))
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}
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when( isCrcPass & downRegTemp(0)(3,0) === 1.U ){
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mthodReg := Cat(downRegTemp(3), downRegTemp(2))
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valueReg := Cat(downRegTemp(5), downRegTemp(4))
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}
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when( statusPage === 0.U ){
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upReg(4) := Cat( ( 3 to 0 by -1).map{ i => chsWire(i) } )
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upReg(5) := Cat( ( 7 to 4 by -1).map{ i => chsWire(i) } )
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upReg(6) := Cat( ( 11 to 8 by -1).map{ i => chsWire(i) } )
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upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
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}
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chsWire := 0.U.asTypeOf(chsWire)
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out := outPin
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}
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