新主站发送逻辑

This commit is contained in:
RuigeLee
2024-10-09 17:37:15 +08:00
parent 58aecc043f
commit a6068fbda0
6 changed files with 207 additions and 4 deletions

View File

@@ -3,15 +3,15 @@ package BACK
import chisel3._
import chisel3.util._
class AXIS_Bundle extends Bundle{
val tdata = UInt(8.W)
class AXIS_Bundle(dw: Int) extends Bundle{
val tdata = UInt(dw.W)
val tlast = Bool()
val tuser = Bool()
}
//work in 100MHZ
class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle))
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val serDat = Output(Bool())
}