新主站发送逻辑
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@@ -3,15 +3,15 @@ package BACK
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import chisel3._
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import chisel3.util._
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class AXIS_Bundle extends Bundle{
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val tdata = UInt(8.W)
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class AXIS_Bundle(dw: Int) extends Bundle{
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val tdata = UInt(dw.W)
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val tlast = Bool()
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val tuser = Bool()
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}
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//work in 100MHZ
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class CDROutIO extends Bundle{
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val axis = Flipped(Decoupled(new AXIS_Bundle))
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val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
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val serDat = Output(Bool())
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}
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