From a6068fbda070eeb4db52585e88d53be4f05f9f29 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 9 Oct 2024 17:37:15 +0800 Subject: [PATCH] =?UTF-8?q?=E6=96=B0=E4=B8=BB=E7=AB=99=E5=8F=91=E9=80=81?= =?UTF-8?q?=E9=80=BB=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/ebus/Axis8toN.scala.bk | 29 +++++ .../scala/backBoard/ebus/AxisNto8.scala.bk | 48 +++++++ src/main/scala/backBoard/ebus/CDRIn.scala | 2 +- src/main/scala/backBoard/ebus/CDROut.scala | 6 +- src/main/scala/backBoard/shin/ShinMst.scala | 120 ++++++++++++++++++ src/main/scala/backBoard/shin/ShinSlv.scala | 6 + 6 files changed, 207 insertions(+), 4 deletions(-) create mode 100644 src/main/scala/backBoard/ebus/Axis8toN.scala.bk create mode 100644 src/main/scala/backBoard/ebus/AxisNto8.scala.bk create mode 100644 src/main/scala/backBoard/shin/ShinMst.scala create mode 100644 src/main/scala/backBoard/shin/ShinSlv.scala diff --git a/src/main/scala/backBoard/ebus/Axis8toN.scala.bk b/src/main/scala/backBoard/ebus/Axis8toN.scala.bk new file mode 100644 index 0000000..4866875 --- /dev/null +++ b/src/main/scala/backBoard/ebus/Axis8toN.scala.bk @@ -0,0 +1,29 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class Axis8toNIO_Bundle(dw: Int) extends Bundle{ + val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(8))) + val deq = Decoupled(new AxisNto8IO_Bundle(dw)) +} + + + + +class Axis8toN(dw: Int) extends Module{ + + require( dw == 16 | dw == 32 | dw == 64 ) + assert( io.deq.ready === true.B ) + + val io: Axis8toNIO_Bundle = IO(new Axis8toNIO_Bundle(dw)) + + val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) ) + + val fifo = Reg( new AxisNto8IO_Bundle(dw) ) + + + +} + diff --git a/src/main/scala/backBoard/ebus/AxisNto8.scala.bk b/src/main/scala/backBoard/ebus/AxisNto8.scala.bk new file mode 100644 index 0000000..d3c64cb --- /dev/null +++ b/src/main/scala/backBoard/ebus/AxisNto8.scala.bk @@ -0,0 +1,48 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class AxisNto8IO_Bundle(dw: Int) extends Bundle{ + val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(dw))) + val deq = Decoupled(new AxisNto8IO_Bundle(8)) +} + + +class AxisNto8(dw: Int) extends Module{ + + require( dw == 16 | dw == 32 | dw == 64 ) + + val io: AxisNto8IO_Bundle = IO(new AxisNto8IO_Bundle(dw)) + + val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) ) + val isBusy = RegInit(false.B) + + val fifo = RegEnable( io.enq.bits, io.enq.fire ) + io.enq.ready := ~isBusy | (io.deq.fire & cnt.andR) + + + + + when( io.deq.fire ){ + cnt := cnt + 1.U + } + + when( io.enq.fire ){ + isBusy := true.B + } .elsewhen( io.deq.fire & cnt.andR ){ + isBusy := false.B + } + + + + + io.deq.valid := isBusy + io.deq.bits.tdata := fifo.tdata >> (cnt << 3) + io.deq.bits.tlast := fifo.tlast & cnt.andR + io.deq.bits.tuser := fifo.tuser & cnt.andR + + +} + diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index ef87fbd..373f7fe 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -6,7 +6,7 @@ import chisel3.util._ //work in 100MHZ class CDRInIO extends Bundle{ - val axis = Decoupled(new AXIS_Bundle) + val axis = Decoupled(new AXIS_Bundle(8)) val serDat = Input(Bool()) val overCLK = Input(Bool()) } diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index 0963b63..aac3cc0 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -3,15 +3,15 @@ package BACK import chisel3._ import chisel3.util._ -class AXIS_Bundle extends Bundle{ - val tdata = UInt(8.W) +class AXIS_Bundle(dw: Int) extends Bundle{ + val tdata = UInt(dw.W) val tlast = Bool() val tuser = Bool() } //work in 100MHZ class CDROutIO extends Bundle{ - val axis = Flipped(Decoupled(new AXIS_Bundle)) + val axis = Flipped(Decoupled(new AXIS_Bundle(8))) val serDat = Output(Bool()) } diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala new file mode 100644 index 0000000..7990160 --- /dev/null +++ b/src/main/scala/backBoard/shin/ShinMst.scala @@ -0,0 +1,120 @@ +package BACK + +import chisel3._ +import chisel3.util._ + +class Header_Info_Bundle extends Bundle{ + val operator = UInt(8.W) + val length = UInt(8.W) + val param = Vec(3, UInt(16.W)) + + def init = operator === 0.U + def sync = operator === 1.U + def boardCast = operator === 2.U + def uniCast = operator === 3.U +} + + + +abstract class ShinMstPhyBase extends Module{ + + val mirrorDown = Module(new MirrorSRAMDP()) + val mirrorUp = Module(new MirrorSRAMDP()) + + + + val cdrOut = Module(new CDROut) + +} + + +trait ShinMstSend{ this: ShinMstPhyBase => + def isSendTrig: Bool + def isRecvEnd: Bool + def isTimeout: Bool + + + val sendStateNext = Wire( UInt(3.W) ) + val sendStateCurr = RegNext( sendStateNext, 0.U ) + + val sendHeader = Wire( new Header_Info_Bundle ) + + val sendCnt = Reg(UInt(10.W)) + + sendStateNext := Mux1H(Seq( + (sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), + (sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCnt === ((sendHeader.getWidth()/8)*2-1).U, 2.U, 1.U ), + (sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCnt === (sendHeader.length << 1) - 1.U, 3.U, 2.U ), + (sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ), + )) + + when( sendStateCurr === 0.U ){ + when( sendStateNext === 1.U ) { + sendCnt := 0.U + } + } .elsewhen( sendStateCurr === 1.U ){ + when( cdrOut.io.axis.fire ){ + sendCnt := Mux( sendStateNext =/= 2.U, sendCnt + 1.U, 0.U ) + } + } .elsewhen( sendStateCurr === 2.U ){ + when( cdrOut.io.axis.fire ){ + sendCnt := Mux( sendStateNext =/= 3.U, sendCnt + 1.U, 0.U ) + } + } + + cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U + cdrOut.io.axis.bits.tdata := + Mux1H(Seq( + ( sendStateCurr === 1.U ) -> sendHeader.asUInt >> (sendCnt << 3), + ( sendStateCurr === 2.U ) -> Mux( sendCnt.extract(0), mirrorDown(7,0), mirrorDown(15,8) ), + )) + cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCnt === (sendHeader.length << 1) - 1.U + cdrOut.io.axis.bits.tuser := false.B + + + +} + +trait ShinMstRecv{ this: ShinMstPhyBase => + +} + + + + +abstract class ShinMstLinkBase extends ShinMstPhyBase +with ShinMstSend +with ShinMstRecv + + + +trait ShinMstInit{ this: ShinMstLinkBase => + +} + +trait ShinMstSync{ this: ShinMstLinkBase => + +} + +trait ShinMstTrans{ this: ShinMstLinkBase => + +} + +trait ShinMstError{ this: ShinMstLinkBase => + +} + +trait ShinMstInterface{ this: ShinMstLinkBase => + +} + + + + +class ShinMst extends ShinMstLinkBase +with ShinMstInit +with ShinMstSync +with ShinMstTrans +with ShinMstError +with ShinMstInterface + diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala new file mode 100644 index 0000000..f658bbb --- /dev/null +++ b/src/main/scala/backBoard/shin/ShinSlv.scala @@ -0,0 +1,6 @@ +package BACK + +import chisel3._ +import chisel3.util._ + +