新主站发送逻辑

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -6,7 +6,7 @@ import chisel3.util._
 
 //work in 100MHZ
 class CDRInIO extends Bundle{
-  val axis = Decoupled(new AXIS_Bundle)
+  val axis = Decoupled(new AXIS_Bundle(8))
   val serDat = Input(Bool())
   val overCLK = Input(Bool())
 }