新主站发送逻辑

src/main/scala/backBoard/ebus/AxisNto8.scala.bk

@@ -0,0 +1,48 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class AxisNto8IO_Bundle(dw: Int) extends Bundle{
+  val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(dw)))
+  val deq = Decoupled(new AxisNto8IO_Bundle(8))
+}
+
+
+class AxisNto8(dw: Int) extends Module{
+
+  require( dw == 16 | dw == 32 | dw == 64 )
+
+  val io: AxisNto8IO_Bundle = IO(new AxisNto8IO_Bundle(dw))
+
+  val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) )
+  val isBusy = RegInit(false.B)
+
+  val fifo = RegEnable( io.enq.bits, io.enq.fire )
+  io.enq.ready := ~isBusy | (io.deq.fire & cnt.andR)
+
+
+
+
+  when( io.deq.fire ){
+    cnt := cnt + 1.U
+  }
+
+  when( io.enq.fire ){
+    isBusy := true.B
+  } .elsewhen( io.deq.fire & cnt.andR ){
+    isBusy := false.B
+  }
+
+
+
+
+  io.deq.valid := isBusy
+  io.deq.bits.tdata := fifo.tdata >> (cnt << 3)
+  io.deq.bits.tlast := fifo.tlast & cnt.andR
+  io.deq.bits.tuser := fifo.tuser & cnt.andR
+
+
+}
+