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clean maxFL

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RuigeLee
2023-10-25 18:01:04 +08:00
parent 09ea816005
commit a59a0d9687
5 changed files with 2 additions and 16 deletions
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src/main/scala/Switch/mac/MacTx.scala
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@@ -16,7 +16,6 @@ class MacTxIO extends Bundle{
val FullD = Input(Bool()) // Full duplex (from register)
val DlyCrcEn = Input(Bool()) // Delayed Crc enabled (from register)
val MinFL = Input(UInt(16.W)) // Minimum frame length (from register)
val MaxFL = Input(UInt(16.W)) // Maximum frame length (from register)
val IPGT = Input(UInt(7.W)) // Back to back transmit inter packet gap parameter (from register)
val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register)
val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)