From a59a0d96872c79c9d564978fb5712d49cc269635 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 25 Oct 2023 18:01:04 +0800 Subject: [PATCH] clean maxFL --- src/main/scala/Switch/MacRegisters.scala | 7 ++----- src/main/scala/Switch/mac/MAC.scala | 7 ------- src/main/scala/Switch/mac/MacRx.scala | 1 - src/main/scala/Switch/mac/MacStatus.scala | 2 -- src/main/scala/Switch/mac/MacTx.scala | 1 - 5 files changed, 2 insertions(+), 16 deletions(-) diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala index e566830..96099a1 100644 --- a/src/main/scala/Switch/MacRegisters.scala +++ b/src/main/scala/Switch/MacRegisters.scala @@ -43,7 +43,6 @@ class Mac_Config_Bundle extends Bundle{ val r_IPGR1 = Output(UInt(7.W)) val r_IPGR2 = Output(UInt(7.W)) val r_MinFL = Output(UInt(16.W)) - val r_MaxFL = Output(UInt(16.W)) val r_CollValid = Output(UInt(6.W)) val r_MiiNoPre = Output(Bool()) val r_ClkDiv = Output(UInt(8.W)) @@ -123,7 +122,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out val IPGR1 = RegInit("h0C".U(7.W)) // IPGR1 Register val IPGR2 = RegInit("h12".U(7.W)) - val maxFL = RegInit("h0600".U(16.W)) val minFL = RegInit("h0040".U(16.W)) val collValid = RegInit("h3f".U(6.W)) @@ -221,8 +219,8 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out )), ( 6 << 2 ) -> - RegFieldGroup("PACKETLEN", Some("Packet Length Register"), - RegField.bytes(maxFL, Some(RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600)))) ++ + RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq( + RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600)))) ++ RegField.bytes(minFL, Some(RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040)))) ), ( 7 << 2 ) -> @@ -348,7 +346,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out io.r_IPGR1 := IPGR1 io.r_IPGR2 := IPGR2 io.r_MinFL := minFL - io.r_MaxFL := maxFL io.r_CollValid := collValid io.r_MiiNoPre := miiNoPre io.r_ClkDiv := clkDiv diff --git a/src/main/scala/Switch/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala index 75003da..aff8043 100644 --- a/src/main/scala/Switch/mac/MAC.scala +++ b/src/main/scala/Switch/mac/MAC.scala @@ -141,7 +141,6 @@ val MRxErr_Lb = Wire(Bool()) val MRxD_Lb = Wire(UInt(4.W)) val Transmitting = Wire(Bool()) val r_DlyCrcEn = Wire(Bool()) -val r_MaxFL = Wire(UInt(16.W)) val r_MinFL = Wire(UInt(16.W)) val DribbleNibble = Wire(Bool()) val LoadRxStatus = Wire(Bool()) @@ -180,7 +179,6 @@ dontTouch(MRxErr_Lb ) dontTouch(MRxD_Lb ) dontTouch(Transmitting ) dontTouch(r_DlyCrcEn ) -dontTouch(r_MaxFL ) dontTouch(r_MinFL ) dontTouch(DribbleNibble ) dontTouch(LoadRxStatus ) @@ -248,7 +246,6 @@ r_IPGT := io.cfg.r_IPGT r_IPGR1 := io.cfg.r_IPGR1 r_IPGR2 := io.cfg.r_IPGR2 r_MinFL := io.cfg.r_MinFL -r_MaxFL := io.cfg.r_MaxFL r_CollValid := io.cfg.r_CollValid r_MiiNoPre := io.cfg.r_MiiNoPre r_ClkDiv := io.cfg.r_ClkDiv @@ -349,7 +346,6 @@ txethmac.io.CrcEn := r_CrcEn | PerPacketCrcEn txethmac.io.FullD := r_FullD txethmac.io.DlyCrcEn := r_DlyCrcEn txethmac.io.MinFL := r_MinFL -txethmac.io.MaxFL := r_MaxFL txethmac.io.IPGT := r_IPGT txethmac.io.IPGR1 := r_IPGR1 txethmac.io.IPGR2 := r_IPGR2 @@ -402,7 +398,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M rxethmac.io.MRxD := MRxD_Lb rxethmac.io.Transmitting := Transmitting rxethmac.io.DlyCrcEn := r_DlyCrcEn - rxethmac.io.MaxFL := r_MaxFL rxethmac.io.r_IFG := r_IFG rxethmac.io.r_HASH0 := r_HASH0 rxethmac.io.r_HASH1 := r_HASH1 @@ -495,8 +490,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M macstatus.io.MRxD := MRxD_Lb macstatus.io.Collision := io.mii.mcoll_pad_i macstatus.io.CollValid := r_CollValid - macstatus.io.r_MinFL := r_MinFL - macstatus.io.r_MaxFL := r_MaxFL macstatus.io.StartTxDone := StartTxDone macstatus.io.StartTxAbort := StartTxAbort macstatus.io.MTxClk := io.mii.mtx_clk_pad_i diff --git a/src/main/scala/Switch/mac/MacRx.scala b/src/main/scala/Switch/mac/MacRx.scala index c98ee4a..b59ca1e 100644 --- a/src/main/scala/Switch/mac/MacRx.scala +++ b/src/main/scala/Switch/mac/MacRx.scala @@ -11,7 +11,6 @@ class MacRxIO extends Bundle{ val MRxD = Input(UInt(4.W)) val Transmitting = Input(Bool()) val DlyCrcEn = Input(Bool()) - val MaxFL = Input(UInt(16.W)) val r_IFG = Input(Bool()) val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table diff --git a/src/main/scala/Switch/mac/MacStatus.scala b/src/main/scala/Switch/mac/MacStatus.scala index e191a69..6c6626d 100644 --- a/src/main/scala/Switch/mac/MacStatus.scala +++ b/src/main/scala/Switch/mac/MacStatus.scala @@ -21,8 +21,6 @@ class MacStatusIO extends Bundle{ val MRxD = Input(UInt(4.W)) val Collision = Input(Bool()) val CollValid = Input(UInt(6.W)) - val r_MinFL = Input(UInt(16.W)) - val r_MaxFL = Input(UInt(16.W)) val StartTxDone = Input(Bool()) val StartTxAbort = Input(Bool()) val MTxClk = Input(Bool()) diff --git a/src/main/scala/Switch/mac/MacTx.scala b/src/main/scala/Switch/mac/MacTx.scala index 4895567..395c2b9 100644 --- a/src/main/scala/Switch/mac/MacTx.scala +++ b/src/main/scala/Switch/mac/MacTx.scala @@ -16,7 +16,6 @@ class MacTxIO extends Bundle{ val FullD = Input(Bool()) // Full duplex (from register) val DlyCrcEn = Input(Bool()) // Delayed Crc enabled (from register) val MinFL = Input(UInt(16.W)) // Minimum frame length (from register) - val MaxFL = Input(UInt(16.W)) // Maximum frame length (from register) val IPGT = Input(UInt(7.W)) // Back to back transmit inter packet gap parameter (from register) val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register) val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)