SM sram化改造，探针改造，写接口
This commit is contained in:
Ruige Lee
@@ -41,8 +41,14 @@ class SlaveParserIO extends Bundle{
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// val sram_r = Flipped(new ShareSRAMIO)
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// val sram_w = Flipped(new ShareSRAMIO)
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val dSMenq = Vec(4, Decoupled(UInt(8.W)))
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val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
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// val dSMenq = Vec(4, Decoupled(UInt(8.W)))
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// val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
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val sram_w = Vec( 4, Flipped(new SRAM2kWRIO) )
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val sram_r = Vec( 4, Flipped(new SRAM2kRDIO) )
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val dSMenq = Input( Vec(4, Bool()) )
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val uSMdeq = Input( Vec(4, Bool()) )
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val timeStamp = Input(UInt(64.W))
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}
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@@ -357,8 +363,14 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
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trait SlaveParserRW{ this: SlaveParserBase =>
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//下行接收
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when( downRecParser.io.subMsgReq.fire ){
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when( isDownRecPing ){
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@@ -377,50 +389,47 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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//写入SM
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//写入 SM或寄存器空间
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val addrw = Reg(UInt(15.W))
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val isWRRegister = (addrw(14,11) === "b0000".U)
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val isWRSM0 = (addrw(14,11) === "b0001".U)
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val isWRSM2 = (addrw(14,11) === "b0011".U)
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val isWRSM4 = (addrw(14,11) === "b0101".U)
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val isWRSM6 = (addrw(14,11) === "b0111".U)
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when( downRecParser.io.subMsgReq.fire ){
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when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
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addrw := downRecParser.io.subMsgReq.bits.address
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}
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}
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val isWriteSM := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
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val isWrite := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
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( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
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( isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
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)
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val isTermSM = Seq[Bool]
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io.dSMenq(0).valid := isWriteSM & addrw === 0.U
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io.dSMenq(0).bits := downRecParser.io.data.bits
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when( io.dSMenq(0).valid & ~io.dSMenq(0).ready ){
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printf("An Error occur at dSMenq0!\n")
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}
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io.dSMenq(1).valid := isWriteSM & addrw === 1.U
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io.dSMenq(1).bits := downRecParser.io.data.bits
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when( io.dSMenq(1).valid & ~io.dSMenq(1).ready ){
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printf("An Error occur at dSMenq1!\n")
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}
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io.dSMenq(2).valid := isWriteSM & addrw === 2.U
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io.dSMenq(2).bits := downRecParser.io.data.bits
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when( io.dSMenq(2).valid & ~io.dSMenq(2).ready ){
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printf("An Error occur at dSMenq2!\n")
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}
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io.dSMenq(3).valid := isWriteSM & addrw === 3.U
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io.dSMenq(3).bits := downRecParser.io.data.bits
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when( io.dSMenq(3).valid & ~io.dSMenq(3).ready ){
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printf("An Error occur at dSMenq3!\n")
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}
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io.sram_w(0).enw := isWrite & isWRSM0
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io.sram_w(0).addrw := addrw(10,0)
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io.sram_w(0).dataw := downRecParser.io.data.bits
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io.sram_w(1).enw := isWrite & isWRSM2
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io.sram_w(1).addrw := addrw(10,0)
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io.sram_w(1).dataw := downRecParser.io.data.bits
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io.sram_w(2).enw := isWrite & isWRSM4
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io.sram_w(2).addrw := addrw(10,0)
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io.sram_w(2).dataw := downRecParser.io.data.bits
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io.sram_w(3).enw := isWrite & isWRSM6
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io.sram_w(3).addrw := addrw(10,0)
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io.sram_w(3).dataw := downRecParser.io.data.bits
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//上行接收
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@@ -444,7 +453,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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//读出uSM
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val isReadSM =
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val isRead =
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((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (upSubMsgInfo(0).devIndex === localDevIndex) & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
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((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
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@@ -454,24 +463,29 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr,
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))
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val isRDRegister = (readSMAddr(14,11) === "b0000".U)
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val isRDSM1 = (readSMAddr(14,11) === "b0010".U)
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val isRDSM3 = (readSMAddr(14,11) === "b0100".U)
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val isRDSM5 = (readSMAddr(14,11) === "b0110".U)
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val isRDSM7 = (readSMAddr(14,11) === "b1000".U)
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when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
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addrr := upRecParser.io.subMsgReq.bits.address
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}
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val uSMData = Mux1H(Seq(
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(readSMAddr === 0.U) -> io.uSMdeq(0).bits,
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(readSMAddr === 1.U) -> io.uSMdeq(1).bits,
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(readSMAddr === 2.U) -> io.uSMdeq(2).bits,
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(readSMAddr === 3.U) -> io.uSMdeq(3).bits,
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val upStreamData = Mux1H(Seq(
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isRDRegister -> ,
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isRDSM1 -> io.sram_r(0).datar,
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isRDSM3 -> io.sram_r(1).datar,
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isRDSM5 -> io.sram_r(2).datar,
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isRDSM7 -> io.sram_r(3).datar,
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))
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when( ~isUpRecPing ){ //req fire 后 已经反相
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upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
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upRecFifo(0).io.enq.bits :=
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Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
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uSMData, upRecParser.io.data.bits)
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upStreamData, upRecParser.io.data.bits)
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upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
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upRecFifo(1).io.enq.valid := false.B
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@@ -483,17 +497,20 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
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upRecFifo(1).io.enq.bits :=
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Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
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uSMData, upRecParser.io.data.bits)
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upStreamData, upRecParser.io.data.bits)
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upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
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}
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io.sram_r(0).enr := isRead & isRDSM1
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io.sram_r(1).enr := isRead & isRDSM3
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io.sram_r(2).enr := isRead & isRDSM5
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io.sram_r(3).enr := isRead & isRDSM7
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io.uSMdeq(0).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 0.U )
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io.uSMdeq(1).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 1.U )
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io.uSMdeq(2).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 2.U )
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io.uSMdeq(3).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 3.U )
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io.sram_r(0).addrr := readSMAddr(10,0)
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io.sram_r(1).addrr := readSMAddr(10,0)
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io.sram_r(2).addrr := readSMAddr(10,0)
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io.sram_r(3).addrr := readSMAddr(10,0)
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}
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@@ -584,32 +601,47 @@ trait SlaveParserSync{ this: SlaveParserBase =>
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trait SlaveParserProbe{ this: SlaveParserBase =>
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val ProbeSendAim = 10000.U
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val ProbeRecAim = 20000.U
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val probeSendCnt = RegInit(0.U(32.W))
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val probeRecCnt = RegInit(0.U(32.W))
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val isReadyToProbe = probeSendCnt === ProbeSendAim
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val isWatchDogOverflow = probeRecCnt === ProbeRecAim
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val isReadyToProbe = RegInit(false.B)
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when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
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isReadyToProbe := true.B
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} .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
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isReadyToProbe := false.B
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} .elsewhen( isWatchDogOverflow ){
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isReadyToProbe := false.B
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}
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val isLastDevice: Bool = RegInit(false.B)
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val isDeviceModified: Bool = RegInit(true.B)
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when( upRecParser.io.frameReq.fire ){ //上行来了一个嗅探包
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when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
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probeRecCnt := 0.U
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isLastDevice := false.B
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} .elsewhen( isWatchDogOverflow ){
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probeRecCnt := 0.U
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isLastDevice := true.B
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} .otherwise{
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} .elsewhen( isReadyToProbe ){
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probeRecCnt := probeRecCnt + 1.U
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}
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when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
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when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){
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when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
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isDeviceModified := true.B
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}
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}
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@@ -619,15 +651,15 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
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io.upOut <> upSendGen.io.send
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io.downIn <> downRecParser.io.rec
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when( isLastDevice & isReadyToProbe ){
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downSendGen.io.send <> upRecParser.io.rec
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when( isLastDevice & ~isReadyToProbe ){ //最后一个设备且不是探测模式
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downSendGen.io.send <> upRecParser.io.rec //axis短接
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io.downOut.valid := false.B
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io.downOut.valid := false.B //对外下级io开路
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io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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io.upIn.ready := false.B
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} .otherwise{
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io.downOut <> downSendGen.io.send
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io.upIn <> upRecParser.io.rec
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