diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index aa25bee..44dc1e5 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -7,25 +7,66 @@ class InterfaceIO extends Module{
 
 }
 
+class MasterRegisterBundle extends Bundle{
+  val isMstNSlv = Bool()
+  val hwVersion = UInt(8.W)
+  val hwSerial  = UInt(48.W)
+  val busRate   = UInt(16.W)
+
+  val isExInfoInit = Bool()
+  val isTxReq      = UInt(8.W)
+  val txStatus     = UInt(16.W)
+  val spiSel       = UInt(2.W)
+
+  val isSoftReset  = Bool()
+  val encryptKey   = UInt(128.W)
+  val isEncrypt    = Bool()
+
+  val intEnable    = UInt(8.W)
+  val intMask      = UInt(8.W)
+  val intStatus    = UInt(8.W)
+
+  val upRecErrorCnt   = UInt(32.W)
+  val downRecErrorCnt = UInt(32.W)
+
+  val upForwardErrorCnt   = UInt(32.W)
+  val downForwardErrorCnt = UInt(32.W)
+
+  val qspiErrorCnt   = UInt(32.W)
+  val forwardCnt     = UInt(32.W)
+  val recByteCnt     = UInt(32.W)
+  val forwardByteCnt = UInt(32.W)
+
+  val linkStatus = UInt(8.W)
+
+  val wdtStatus   = UInt(16.W)
+  val wdtOverflow = UInt(8.W)
+
+  val timeStamp = UInt(64.W)
+  val deltaTime = UInt(32.W)
+}
+
+
+
+
 abstract class InterfaceBase extends Module{
   val io: InterfaceIO = IO(new InterfaceIO)
 
 
 
-  val isMstNSlv: Bool
-  val hwVersion: UInt
-  val hwSerial: UInt
-  val busRate: UInt
-  val RAMSize: UInt
-  val MMUNum: UInt
 
-  val nodeSeqAddr = Reg(UInt(16.W))
-  val nodeSetAddr = Reg(UInt(16.W))
 
-  val softReset = Reg(Bool())
-  val logicAddr = Reg(UInt(30.W))
-  val logicLength = Reg(UInt(16.W))
-  val phyAddr - Reg(UInt(16.W))
+
+  // val RAMSize: UInt
+  // val MMUNum: UInt
+
+  // val nodeSeqAddr = Reg(UInt(16.W))
+  // val nodeSetAddr = Reg(UInt(16.W))
+
+  // val softReset = Reg(Bool())
+  // val logicAddr = Reg(UInt(30.W))
+  // val logicLength = Reg(UInt(16.W))
+  // val phyAddr - Reg(UInt(16.W))
 
 
 }
diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala
index 2e50e20..d068615 100644
--- a/src/main/scala/backBoard/shin/SMUnit.scala
+++ b/src/main/scala/backBoard/shin/SMUnit.scala
@@ -3,177 +3,96 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-class SMUnitIO extends Bundle {
-  val maxLen = Input(UInt(11.W))
-  val enq = Flipped(Decoupled(UInt(8.W)))
-  val deq = Decoupled(UInt(8.W))
 
-  val sram = Vec(4, new SRAM2kIO)
+// class SRAM2kWRIO extends Bundle {
+//   val addrw = Output(UInt(11.W))
+//   val dataw = Output( UInt(8.W) )
+//   val enw   = Output(Bool())
+// }
+
+// class SRAM2kRDIO extends Bundle {
+//   val addrr = Output(UInt(11.W))
+//   val datar = Input( UInt(8.W) )
+//   val enr   = Output(Bool())
+// }
+
+// class SRAM2kIO extends Bundle {
+//   val addrr  = Output(UInt(11.W))
+//   val addrw  = Output(UInt(11.W))
+
+//   val dataw = Output( UInt(8.W) )
+//   val datar = Input( UInt(8.W) )
+//   val enw   = Output(Bool())
+//   val enr   = Output(Bool())
+// }
+
+class SMUnitIO(depth: Int) extends Bundle {
+
+  val sram_w = Flipped(new SRAM2kWRIO)
+  val sram_r = Flipped(new SRAM2kRDIO)
+
+  val enq = Input(Bool())
+  val deq = Input(Bool())
+
+  val sram = Vec(depth, new SRAM2kIO)
 
 }
 
-abstract class SMUnitBase extends Module {
-  val io: SMUnitIO = IO(new SMUnitIO)
+abstract class SMUnitBase(depth: Int = 4) extends Module {
+  val io: SMUnitIO = IO(new SMUnitIO(depth))
+ 
 
-  val enqCnt = Reg(UInt(11.W))
-  val deqCnt = Reg(UInt(11.W))
+  val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
+  val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
 
-
-
-
-
-  val dataBuf =
-    for ( i <- 0 until 4 ) yield {
-      val mdl = Module( new SRAM2kFifo )
-      io.sram(i) <> mdl.io.sram
-      mdl
-    }
-
-  
-
-  val wPtr = RegInit(0.U((2+1).W))
-  val rPtr = RegInit(0.U((2+1).W))
-
-  val isFull =
-    ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )
+  val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
+    // ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )
 
 
   val isEmpty = ( wPtr === rPtr )
 
-  when( io.enq.fire ){
-    when( enqCnt === io.maxLen ){
-      enqCnt := 0.U
-    } .otherwise{
-      enqCnt := enqCnt + 1.U
-    }
-  }
 
-  when( io.deq.fire ){
-    when( deqCnt === io.maxLen ){
-      deqCnt := 0.U
-    } .otherwise{
-      deqCnt := deqCnt + 1.U
-    }
-  }
-
-
-  when( io.enq.fire & enqCnt === io.maxLen ){
+  when( io.enq ){
     wPtr := wPtr + 1.U
   }
 
-  when( io.deq.fire & deqCnt === io.maxLen ){
+  when( io.deq ){
     rPtr := rPtr + 1.U
   }
 
+  for( i <- 0 until depth ){
+    io.sram(i).addrw := 0.U
+    io.sram(i).dataw := 0.U
+    io.sram(i).enw   := false.B
 
-  when( wPtr === 0.U & ~isFull ){
-    dataBuf(0).io.enq.valid := io.enq.valid
-    dataBuf(0).io.enq.bits  := io.enq.bits
-    io.enq.ready := dataBuf(0).io.enq.ready
-
-    dataBuf(1).io.enq.valid := false.B
-    dataBuf(1).io.enq.bits  := 0.U
-    dataBuf(2).io.enq.valid := false.B
-    dataBuf(2).io.enq.bits  := 0.U
-    dataBuf(3).io.enq.valid := false.B
-    dataBuf(3).io.enq.bits  := 0.U
-  } .elsewhen( wPtr === 1.U & ~isFull ){
-    dataBuf(1).io.enq.valid := io.enq.valid
-    dataBuf(1).io.enq.bits  := io.enq.bits
-    io.enq.ready := dataBuf(1).io.enq.ready
-
-    dataBuf(0).io.enq.valid := false.B
-    dataBuf(0).io.enq.bits  := 0.U
-    dataBuf(2).io.enq.valid := false.B
-    dataBuf(2).io.enq.bits  := 0.U
-    dataBuf(3).io.enq.valid := false.B
-    dataBuf(3).io.enq.bits  := 0.U
-  } .elsewhen( wPtr === 2.U & ~isFull ){
-    dataBuf(2).io.enq.valid := io.enq.valid
-    dataBuf(2).io.enq.bits  := io.enq.bits
-    io.enq.ready := dataBuf(2).io.enq.ready
-
-    dataBuf(0).io.enq.valid := false.B
-    dataBuf(0).io.enq.bits  := 0.U
-    dataBuf(1).io.enq.valid := false.B
-    dataBuf(1).io.enq.bits  := 0.U
-    dataBuf(3).io.enq.valid := false.B
-    dataBuf(3).io.enq.bits  := 0.U
-  } .elsewhen( wPtr === 3.U & ~isFull ){
-    dataBuf(3).io.enq.valid := io.enq.valid
-    dataBuf(3).io.enq.bits  := io.enq.bits
-    io.enq.ready := dataBuf(3).io.enq.ready
-
-    dataBuf(0).io.enq.valid := false.B
-    dataBuf(0).io.enq.bits  := 0.U
-    dataBuf(1).io.enq.valid := false.B
-    dataBuf(1).io.enq.bits  := 0.U
-    dataBuf(2).io.enq.valid := false.B
-    dataBuf(2).io.enq.bits  := 0.U
-
-  } .otherwise{
-
-    io.enq.ready := false.B
-
-    dataBuf(0).io.enq.valid := false.B
-    dataBuf(0).io.enq.bits  := 0.U
-    dataBuf(1).io.enq.valid := false.B
-    dataBuf(1).io.enq.bits  := 0.U
-    dataBuf(2).io.enq.valid := false.B
-    dataBuf(2).io.enq.bits  := 0.U
-    dataBuf(3).io.enq.valid := false.B
-    dataBuf(3).io.enq.bits  := 0.U
+    io.sram(i).addrr := 0.U
+    io.sram(i).enr   := false.B
   }
 
-  when( rPtr === 0.U & ~isEmpty){
-    io.deq.valid := dataBuf(0).io.deq.valid
-    io.deq.bits  := dataBuf(0).io.deq.bits
+  for( i <- 0 until depth ){
+    when( wPtr === i.U & ~isFull ){
+      io.sram(i).addrw := io.sram_w.addrw
+      io.sram(i).dataw := io.sram_w.dataw
+      io.sram(i).enw   := io.sram_w.enw
+    }
 
-    dataBuf(0).io.deq.ready := io.deq.ready
-    dataBuf(1).io.deq.ready := false.B
-    dataBuf(2).io.deq.ready := false.B
-    dataBuf(3).io.deq.ready := false.B
-  } .elsewhen( rPtr === 1.U & ~isEmpty){
-    io.deq.valid := dataBuf(1).io.deq.valid
-    io.deq.bits  := dataBuf(1).io.deq.bits
-
-    dataBuf(0).io.deq.ready := false.B
-    dataBuf(1).io.deq.ready := io.deq.ready
-    dataBuf(2).io.deq.ready := false.B
-    dataBuf(3).io.deq.ready := false.B
-  } .elsewhen( rPtr === 2.U & ~isEmpty){
-    io.deq.valid := dataBuf(2).io.deq.valid
-    io.deq.bits  := dataBuf(2).io.deq.bits
-    
-    dataBuf(0).io.deq.ready := false.B
-    dataBuf(1).io.deq.ready := false.B
-    dataBuf(2).io.deq.ready := io.deq.ready
-    dataBuf(3).io.deq.ready := false.B
-  } .elsewhen( rPtr === 3.U & ~isEmpty){
-    io.deq.valid := dataBuf(3).io.deq.valid
-    io.deq.bits  := dataBuf(3).io.deq.bits
-    
-    dataBuf(0).io.deq.ready := false.B
-    dataBuf(1).io.deq.ready := false.B
-    dataBuf(2).io.deq.ready := false.B
-    dataBuf(3).io.deq.ready := io.deq.ready
-  } .otherwise{
-    io.deq.valid := false.B
-    io.deq.bits  := 0.U
-    
-    dataBuf(0).io.deq.ready := false.B
-    dataBuf(1).io.deq.ready := false.B
-    dataBuf(2).io.deq.ready := false.B
-    dataBuf(3).io.deq.ready := io.deq.ready
+    when( rPtr === i.U & ~isEmpty){
+      io.sram(i).addrr := io.sram_r.addrr
+      io.sram(i).enr   := io.sram_r.enr
+    }
   }
 
 
 
+  io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
+    ( rPtr === i.U ) -> io.sram(i).datar,
+  })
+
 
 
 }
 
-class SMUnit extends SMUnitBase {
+class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {
 
 
 }
diff --git a/src/main/scala/backBoard/shin/SRAMFifo.scala b/src/main/scala/backBoard/shin/SRAMFifo.scala
index 93c65d3..19f15a4 100644
--- a/src/main/scala/backBoard/shin/SRAMFifo.scala
+++ b/src/main/scala/backBoard/shin/SRAMFifo.scala
@@ -3,6 +3,19 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+class SRAM2kWRIO extends Bundle {
+  val addrw = Output(UInt(11.W))
+  val dataw = Output( UInt(8.W) )
+  val enw   = Output(Bool())
+}
+
+class SRAM2kRDIO extends Bundle {
+  val addrr = Output(UInt(11.W))
+  val datar = Input( UInt(8.W) )
+  val enr   = Output(Bool())
+}
+
+
 class SRAM2kIO extends Bundle {
   val addrr  = Output(UInt(11.W))
   val addrw  = Output(UInt(11.W))
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index c0964a8..2769021 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -41,8 +41,14 @@ class SlaveParserIO extends Bundle{
   // val sram_r = Flipped(new ShareSRAMIO)
   // val sram_w = Flipped(new ShareSRAMIO)
 
-  val dSMenq = Vec(4, Decoupled(UInt(8.W)))
-  val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
+  // val dSMenq = Vec(4, Decoupled(UInt(8.W)))
+  // val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
+
+  val sram_w = Vec( 4, Flipped(new SRAM2kWRIO) )
+  val sram_r = Vec( 4, Flipped(new SRAM2kRDIO) )
+
+  val dSMenq = Input( Vec(4, Bool()) )
+  val uSMdeq = Input( Vec(4, Bool()) )
 
   val timeStamp = Input(UInt(64.W))
 }
@@ -357,8 +363,14 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
 
 
 
+
+
 trait SlaveParserRW{ this: SlaveParserBase =>
 
+
+
+
+
   //下行接收
   when( downRecParser.io.subMsgReq.fire ){
     when( isDownRecPing ){
@@ -377,50 +389,47 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
 
 
-  //写入SM
+  //写入 SM或寄存器空间
 
   val addrw = Reg(UInt(15.W))
 
+  val isWRRegister = (addrw(14,11) === "b0000".U)
+  val isWRSM0      = (addrw(14,11) === "b0001".U)
+  val isWRSM2      = (addrw(14,11) === "b0011".U)
+  val isWRSM4      = (addrw(14,11) === "b0101".U)
+  val isWRSM6      = (addrw(14,11) === "b0111".U)
+
+
+
   when( downRecParser.io.subMsgReq.fire ){
     when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
       addrw := downRecParser.io.subMsgReq.bits.address
     }
   }
 
-  val isWriteSM := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
+  val isWrite := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
     ( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
     (  isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
   )
 
 
+    val isTermSM = Seq[Bool]
 
-  io.dSMenq(0).valid := isWriteSM & addrw === 0.U
-  io.dSMenq(0).bits  := downRecParser.io.data.bits
-  when( io.dSMenq(0).valid & ~io.dSMenq(0).ready ){
-    printf("An Error occur at dSMenq0!\n")
-  }
-
-  io.dSMenq(1).valid := isWriteSM & addrw === 1.U
-  io.dSMenq(1).bits  := downRecParser.io.data.bits
-  when( io.dSMenq(1).valid & ~io.dSMenq(1).ready ){
-    printf("An Error occur at dSMenq1!\n")
-  }
-
-  io.dSMenq(2).valid := isWriteSM & addrw === 2.U
-  io.dSMenq(2).bits  := downRecParser.io.data.bits
-  when( io.dSMenq(2).valid & ~io.dSMenq(2).ready ){
-    printf("An Error occur at dSMenq2!\n")
-  }
-
-  io.dSMenq(3).valid := isWriteSM & addrw === 3.U
-  io.dSMenq(3).bits  := downRecParser.io.data.bits
-  when( io.dSMenq(3).valid & ~io.dSMenq(3).ready ){
-    printf("An Error occur at dSMenq3!\n")
-  }
-
+    io.sram_w(0).enw   := isWrite & isWRSM0
+    io.sram_w(0).addrw := addrw(10,0)
+    io.sram_w(0).dataw := downRecParser.io.data.bits
 
+    io.sram_w(1).enw   := isWrite & isWRSM2
+    io.sram_w(1).addrw := addrw(10,0)
+    io.sram_w(1).dataw := downRecParser.io.data.bits
 
+    io.sram_w(2).enw   := isWrite & isWRSM4
+    io.sram_w(2).addrw := addrw(10,0)
+    io.sram_w(2).dataw := downRecParser.io.data.bits
 
+    io.sram_w(3).enw   := isWrite & isWRSM6
+    io.sram_w(3).addrw := addrw(10,0)
+    io.sram_w(3).dataw := downRecParser.io.data.bits
 
 
   //上行接收
@@ -444,7 +453,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
 
   //读出uSM  
-  val isReadSM = 
+  val isRead = 
     ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (upSubMsgInfo(0).devIndex === localDevIndex) & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
     ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
 
@@ -454,24 +463,29 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
   ))
 
-
+  val isRDRegister = (readSMAddr(14,11) === "b0000".U)
+  val isRDSM1      = (readSMAddr(14,11) === "b0010".U)
+  val isRDSM3      = (readSMAddr(14,11) === "b0100".U)
+  val isRDSM5      = (readSMAddr(14,11) === "b0110".U)
+  val isRDSM7      = (readSMAddr(14,11) === "b1000".U)
 
   when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
     addrr := upRecParser.io.subMsgReq.bits.address
   }
 
-  val uSMData = Mux1H(Seq(
-    (readSMAddr === 0.U) -> io.uSMdeq(0).bits,
-    (readSMAddr === 1.U) -> io.uSMdeq(1).bits,
-    (readSMAddr === 2.U) -> io.uSMdeq(2).bits,
-    (readSMAddr === 3.U) -> io.uSMdeq(3).bits,
+  val upStreamData = Mux1H(Seq(
+    isRDRegister -> ,
+    isRDSM1      -> io.sram_r(0).datar,
+    isRDSM3      -> io.sram_r(1).datar,
+    isRDSM5      -> io.sram_r(2).datar,
+    isRDSM7      -> io.sram_r(3).datar,
   ))
 
   when( ~isUpRecPing ){ //req fire 后 已经反相
     upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(0).io.enq.bits  := 
       Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
-        uSMData, upRecParser.io.data.bits)
+        upStreamData, upRecParser.io.data.bits)
     upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
 
     upRecFifo(1).io.enq.valid := false.B
@@ -483,17 +497,20 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(1).io.enq.bits  :=
       Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
-        uSMData, upRecParser.io.data.bits)
+        upStreamData, upRecParser.io.data.bits)
     upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
 
   }
 
+  io.sram_r(0).enr := isRead & isRDSM1
+  io.sram_r(1).enr := isRead & isRDSM3
+  io.sram_r(2).enr := isRead & isRDSM5
+  io.sram_r(3).enr := isRead & isRDSM7
 
-  io.uSMdeq(0).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 0.U )
-  io.uSMdeq(1).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 1.U )
-  io.uSMdeq(2).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 2.U )
-  io.uSMdeq(3).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 3.U )
-
+  io.sram_r(0).addrr := readSMAddr(10,0)
+  io.sram_r(1).addrr := readSMAddr(10,0)
+  io.sram_r(2).addrr := readSMAddr(10,0)
+  io.sram_r(3).addrr := readSMAddr(10,0)
 }
 
 
@@ -584,32 +601,47 @@ trait SlaveParserSync{ this: SlaveParserBase =>
 
 trait SlaveParserProbe{ this: SlaveParserBase =>
 
-  val ProbeSendAim = 10000.U
+
   val ProbeRecAim  = 20000.U
-
-
-  val probeSendCnt = RegInit(0.U(32.W))
   val probeRecCnt = RegInit(0.U(32.W))
-
-
-  val isReadyToProbe     = probeSendCnt === ProbeSendAim
   val isWatchDogOverflow = probeRecCnt  === ProbeRecAim
+
+
+
+
+
+  val isReadyToProbe = RegInit(false.B)
+
+  when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
+    isReadyToProbe := true.B
+  } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
+    isReadyToProbe := false.B
+  } .elsewhen( isWatchDogOverflow ){
+    isReadyToProbe := false.B
+  }
+
+
+
+
+
+
+
   val isLastDevice: Bool = RegInit(false.B)
   val isDeviceModified: Bool = RegInit(true.B)
 
-  when( upRecParser.io.frameReq.fire ){ //上行来了一个嗅探包
+  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
     probeRecCnt := 0.U
     isLastDevice := false.B
   } .elsewhen( isWatchDogOverflow ){
     probeRecCnt := 0.U
     isLastDevice := true.B
-  } .otherwise{
+  } .elsewhen( isReadyToProbe ){
     probeRecCnt := probeRecCnt + 1.U
   }
 
 
   when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
-    when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){
+    when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
       isDeviceModified := true.B
     }
   }
@@ -619,15 +651,15 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
   io.upOut   <> upSendGen.io.send
   io.downIn  <> downRecParser.io.rec
 
-  when( isLastDevice & isReadyToProbe ){
-    downSendGen.io.send <> upRecParser.io.rec
+  when( isLastDevice & ~isReadyToProbe ){    //最后一个设备且不是探测模式
+    downSendGen.io.send <> upRecParser.io.rec  //axis短接
 
-    io.downOut.valid := false.B
+    io.downOut.valid := false.B                //对外下级io开路
     io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
     io.upIn.ready := false.B
 
   } .otherwise{
-    
+
     io.downOut <> downSendGen.io.send
     io.upIn    <> upRecParser.io.rec