SM sram化改造，探针改造，写接口

src/main/scala/backBoard/shin/SRAMFifo.scala

@@ -3,6 +3,19 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+class SRAM2kWRIO extends Bundle {
+  val addrw = Output(UInt(11.W))
+  val dataw = Output( UInt(8.W) )
+  val enw   = Output(Bool())
+}
+
+class SRAM2kRDIO extends Bundle {
+  val addrr = Output(UInt(11.W))
+  val datar = Input( UInt(8.W) )
+  val enr   = Output(Bool())
+}
+
+
 class SRAM2kIO extends Bundle {
   val addrr  = Output(UInt(11.W))
   val addrw  = Output(UInt(11.W))