SM sram化改造，探针改造，写接口
This commit is contained in:
Ruige Lee
@@ -3,177 +3,96 @@ package BACK
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import chisel3._
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import chisel3.util._
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class SMUnitIO extends Bundle {
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val maxLen = Input(UInt(11.W))
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val enq = Flipped(Decoupled(UInt(8.W)))
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val deq = Decoupled(UInt(8.W))
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val sram = Vec(4, new SRAM2kIO)
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// class SRAM2kWRIO extends Bundle {
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// val addrw = Output(UInt(11.W))
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// val dataw = Output( UInt(8.W) )
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// val enw = Output(Bool())
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// }
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// class SRAM2kRDIO extends Bundle {
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// val addrr = Output(UInt(11.W))
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// val datar = Input( UInt(8.W) )
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// val enr = Output(Bool())
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// }
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// class SRAM2kIO extends Bundle {
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// val addrr = Output(UInt(11.W))
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// val addrw = Output(UInt(11.W))
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// val dataw = Output( UInt(8.W) )
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// val datar = Input( UInt(8.W) )
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// val enw = Output(Bool())
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// val enr = Output(Bool())
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// }
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class SMUnitIO(depth: Int) extends Bundle {
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val sram_w = Flipped(new SRAM2kWRIO)
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val sram_r = Flipped(new SRAM2kRDIO)
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val enq = Input(Bool())
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val deq = Input(Bool())
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val sram = Vec(depth, new SRAM2kIO)
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}
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abstract class SMUnitBase extends Module {
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val io: SMUnitIO = IO(new SMUnitIO)
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abstract class SMUnitBase(depth: Int = 4) extends Module {
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val io: SMUnitIO = IO(new SMUnitIO(depth))
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val enqCnt = Reg(UInt(11.W))
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val deqCnt = Reg(UInt(11.W))
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val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
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val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
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val dataBuf =
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for ( i <- 0 until 4 ) yield {
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val mdl = Module( new SRAM2kFifo )
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io.sram(i) <> mdl.io.sram
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mdl
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}
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val wPtr = RegInit(0.U((2+1).W))
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val rPtr = RegInit(0.U((2+1).W))
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val isFull =
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( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )
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val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
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// ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )
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val isEmpty = ( wPtr === rPtr )
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when( io.enq.fire ){
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when( enqCnt === io.maxLen ){
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enqCnt := 0.U
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} .otherwise{
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enqCnt := enqCnt + 1.U
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}
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}
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when( io.deq.fire ){
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when( deqCnt === io.maxLen ){
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deqCnt := 0.U
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} .otherwise{
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deqCnt := deqCnt + 1.U
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}
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}
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when( io.enq.fire & enqCnt === io.maxLen ){
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when( io.enq ){
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wPtr := wPtr + 1.U
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}
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when( io.deq.fire & deqCnt === io.maxLen ){
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when( io.deq ){
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rPtr := rPtr + 1.U
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}
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for( i <- 0 until depth ){
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io.sram(i).addrw := 0.U
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io.sram(i).dataw := 0.U
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io.sram(i).enw := false.B
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when( wPtr === 0.U & ~isFull ){
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dataBuf(0).io.enq.valid := io.enq.valid
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dataBuf(0).io.enq.bits := io.enq.bits
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io.enq.ready := dataBuf(0).io.enq.ready
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dataBuf(1).io.enq.valid := false.B
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dataBuf(1).io.enq.bits := 0.U
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dataBuf(2).io.enq.valid := false.B
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dataBuf(2).io.enq.bits := 0.U
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dataBuf(3).io.enq.valid := false.B
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dataBuf(3).io.enq.bits := 0.U
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} .elsewhen( wPtr === 1.U & ~isFull ){
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dataBuf(1).io.enq.valid := io.enq.valid
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dataBuf(1).io.enq.bits := io.enq.bits
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io.enq.ready := dataBuf(1).io.enq.ready
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dataBuf(0).io.enq.valid := false.B
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dataBuf(0).io.enq.bits := 0.U
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dataBuf(2).io.enq.valid := false.B
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dataBuf(2).io.enq.bits := 0.U
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dataBuf(3).io.enq.valid := false.B
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dataBuf(3).io.enq.bits := 0.U
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} .elsewhen( wPtr === 2.U & ~isFull ){
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dataBuf(2).io.enq.valid := io.enq.valid
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dataBuf(2).io.enq.bits := io.enq.bits
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io.enq.ready := dataBuf(2).io.enq.ready
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dataBuf(0).io.enq.valid := false.B
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dataBuf(0).io.enq.bits := 0.U
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dataBuf(1).io.enq.valid := false.B
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dataBuf(1).io.enq.bits := 0.U
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dataBuf(3).io.enq.valid := false.B
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dataBuf(3).io.enq.bits := 0.U
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} .elsewhen( wPtr === 3.U & ~isFull ){
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dataBuf(3).io.enq.valid := io.enq.valid
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dataBuf(3).io.enq.bits := io.enq.bits
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io.enq.ready := dataBuf(3).io.enq.ready
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dataBuf(0).io.enq.valid := false.B
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dataBuf(0).io.enq.bits := 0.U
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dataBuf(1).io.enq.valid := false.B
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dataBuf(1).io.enq.bits := 0.U
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dataBuf(2).io.enq.valid := false.B
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dataBuf(2).io.enq.bits := 0.U
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} .otherwise{
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io.enq.ready := false.B
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dataBuf(0).io.enq.valid := false.B
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dataBuf(0).io.enq.bits := 0.U
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dataBuf(1).io.enq.valid := false.B
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dataBuf(1).io.enq.bits := 0.U
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dataBuf(2).io.enq.valid := false.B
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dataBuf(2).io.enq.bits := 0.U
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dataBuf(3).io.enq.valid := false.B
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dataBuf(3).io.enq.bits := 0.U
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io.sram(i).addrr := 0.U
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io.sram(i).enr := false.B
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}
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when( rPtr === 0.U & ~isEmpty){
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io.deq.valid := dataBuf(0).io.deq.valid
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io.deq.bits := dataBuf(0).io.deq.bits
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for( i <- 0 until depth ){
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when( wPtr === i.U & ~isFull ){
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io.sram(i).addrw := io.sram_w.addrw
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io.sram(i).dataw := io.sram_w.dataw
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io.sram(i).enw := io.sram_w.enw
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}
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dataBuf(0).io.deq.ready := io.deq.ready
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dataBuf(1).io.deq.ready := false.B
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dataBuf(2).io.deq.ready := false.B
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dataBuf(3).io.deq.ready := false.B
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} .elsewhen( rPtr === 1.U & ~isEmpty){
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io.deq.valid := dataBuf(1).io.deq.valid
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io.deq.bits := dataBuf(1).io.deq.bits
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dataBuf(0).io.deq.ready := false.B
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dataBuf(1).io.deq.ready := io.deq.ready
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dataBuf(2).io.deq.ready := false.B
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dataBuf(3).io.deq.ready := false.B
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} .elsewhen( rPtr === 2.U & ~isEmpty){
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io.deq.valid := dataBuf(2).io.deq.valid
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io.deq.bits := dataBuf(2).io.deq.bits
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dataBuf(0).io.deq.ready := false.B
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dataBuf(1).io.deq.ready := false.B
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dataBuf(2).io.deq.ready := io.deq.ready
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dataBuf(3).io.deq.ready := false.B
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} .elsewhen( rPtr === 3.U & ~isEmpty){
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io.deq.valid := dataBuf(3).io.deq.valid
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io.deq.bits := dataBuf(3).io.deq.bits
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dataBuf(0).io.deq.ready := false.B
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dataBuf(1).io.deq.ready := false.B
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dataBuf(2).io.deq.ready := false.B
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dataBuf(3).io.deq.ready := io.deq.ready
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} .otherwise{
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io.deq.valid := false.B
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io.deq.bits := 0.U
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dataBuf(0).io.deq.ready := false.B
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dataBuf(1).io.deq.ready := false.B
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dataBuf(2).io.deq.ready := false.B
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dataBuf(3).io.deq.ready := io.deq.ready
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when( rPtr === i.U & ~isEmpty){
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io.sram(i).addrr := io.sram_r.addrr
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io.sram(i).enr := io.sram_r.enr
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}
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}
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io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
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( rPtr === i.U ) -> io.sram(i).datar,
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})
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}
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class SMUnit extends SMUnitBase {
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class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {
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}
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