语法清理1

src/main/scala/backBoard/shin/ShinSlv.scala

@@ -26,6 +26,8 @@ class ShinSlvIO_Bundle extends Bundle{
 }
 
 abstract class ShinSlvPhyBase extends Module{
+  val io: ShinSlvIO_Bundle = IO(new ShinSlvIO_Bundle)
+
   val downStreamCdrOut = Module(new CDROut)
   val downStreamCdrIn  = Module(new CDRIn )
 
@@ -46,7 +48,7 @@ abstract class ShinSlvPhyBase extends Module{
   val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
   val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
 
-  val headByte = Header_Info_Bundle.getWidth()/8
+  val headByte = (new Header_Info_Bundle).getWidth()/8
   require( headByte == 8 )
   require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n") 
 
@@ -108,7 +110,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
   //---------------
 
   when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){
-    downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
+    downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.bits.tdata ).asTypeOf(new Header_Info_Bundle)
   }
 
 
@@ -122,7 +124,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
 
 
   when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){
-    downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata
+    downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.bits.tdata
   }
 
   //---------------
@@ -146,10 +148,10 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
   } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateIdle ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
-  } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateIdle ){
+  } .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateIdle ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
-  } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateIdle ){
+  } .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvSteteNext === DownRecvStateIdle ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
   } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
@@ -215,7 +217,7 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
   assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )  
 }
 
-abstract ShinSlvPhyDownStream extends ShinSlvPhyBase
+abstract class ShinSlvPhyDownStream extends ShinSlvPhyBase
 with ShinSlvPhyDownStreamRecv
 with ShinSlvPhyDownStreamSend{
   
@@ -507,7 +509,7 @@ class ShinSlvBase extends ShinSlvLinkBase
 with ShinSlvLinkInit
 with ShinSlvLinkBCast
 with ShinSlvLinkUCast{
-  assert( VecInit(upRegMuxInit).contains((x:Bool) = > (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" )
+  assert( VecInit(upRegMuxInit).count((x:Bool) => (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" )
 }