From a44cae1ec39075d407032583ad278fd7cc6edceb Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 15 Oct 2024 17:45:42 +0800 Subject: [PATCH] =?UTF-8?q?=E8=AF=AD=E6=B3=95=E6=B8=85=E7=90=861?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/ShinMst.scala | 24 ++++++++++----------- src/main/scala/backBoard/shin/ShinSlv.scala | 16 ++++++++------ 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala index 383c574..75bd8b1 100644 --- a/src/main/scala/backBoard/shin/ShinMst.scala +++ b/src/main/scala/backBoard/shin/ShinMst.scala @@ -74,7 +74,7 @@ abstract class ShinMstPhyBase extends Module{ trait ShinMstSend{ this: ShinMstPhyBase => - val headByte = Header_Info_Bundle.getWidth()/8 + val headByte = new Header_Info_Bundle.getWidth()/8 require( headByte == 8 ) @@ -91,19 +91,19 @@ trait ShinMstSend{ this: ShinMstPhyBase => mirrorReg.io.addrB := 1.U mirrorReg.io.enrB := true.B - sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle) + sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle) } .elsewhen( ~testIOShift(2) & testIOShift(1) ){ mirrorReg.io.addrB := 2.U mirrorReg.io.enrB := true.B - sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle) + sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle) } .elsewhen( ~testIOShift(3) & testIOShift(2) ){ mirrorReg.io.addrB := 3.U mirrorReg.io.enrB := true.B - sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle) + sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle) } .elsewhen( ~testIOShift(4) & testIOShift(3) ){ - sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle) + sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle) } @@ -132,8 +132,8 @@ trait ShinMstSend{ this: ShinMstPhyBase => sendCntNext := Mux1H(Seq( (sendStateCurr === 0.U) -> 0.U, - (sendStateCurr === 1.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 2.U, sendCnt + 1.U, 0.U ), sendCntCurr), - (sendStateCurr === 2.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 3.U, sendCnt + 1.U, 0.U ), sendCntCurr), + (sendStateCurr === 1.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 2.U, sendCntCurr + 1.U, 0.U ), sendCntCurr), + (sendStateCurr === 2.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 3.U, sendCntCurr + 1.U, 0.U ), sendCntCurr), )) @@ -141,7 +141,7 @@ trait ShinMstSend{ this: ShinMstPhyBase => cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U cdrOut.io.axis.bits.tdata := Mux1H(Seq( - ( sendStateCurr === 1.U ) -> sendHeader.asUInt >> (sendCntCurr << 3), + ( sendStateCurr === 1.U ) -> (sendHeader.asUInt >> (sendCntCurr << 3)), ( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ), )) cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length << 1) - 1.U @@ -161,17 +161,17 @@ trait ShinMstRecv{ this: ShinMstPhyBase => val recvStateNext = Wire( UInt(3.W) ) val recvStateCurr = RegNext( recvStateNext, 0.U ) - val recvHeader = Reg( UInt( Header_Info_Bundle.getWidth.W) ) + val recvHeader = Reg( UInt( (new Header_Info_Bundle).getWidth.W) ) val recvCnt = Reg(UInt(10.W)) - val recvLength = recvHeader.asTypeof(Header_Info_Bundle).length + val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length val isRecvEnd = recvStateCurr === 4.U io.interrupt := recvStateCurr === 4.U - recvStateNext := Mux1h(Seq( + recvStateNext := Mux1H(Seq( (recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE (recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm (recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth()/8-1)*2).U, 3.U, 2.U ), //Header @@ -223,7 +223,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase => - val ( _, isTimeout ) = Counter( range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U ) + val ( _, isTimeout ) = Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U ) } diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala index 9bbf416..03afe06 100644 --- a/src/main/scala/backBoard/shin/ShinSlv.scala +++ b/src/main/scala/backBoard/shin/ShinSlv.scala @@ -26,6 +26,8 @@ class ShinSlvIO_Bundle extends Bundle{ } abstract class ShinSlvPhyBase extends Module{ + val io: ShinSlvIO_Bundle = IO(new ShinSlvIO_Bundle) + val downStreamCdrOut = Module(new CDROut) val downStreamCdrIn = Module(new CDRIn ) @@ -46,7 +48,7 @@ abstract class ShinSlvPhyBase extends Module{ val downRegTemp = Reg(Vec( 32, UInt(8.W) )) val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) - val headByte = Header_Info_Bundle.getWidth()/8 + val headByte = (new Header_Info_Bundle).getWidth()/8 require( headByte == 8 ) require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n") @@ -108,7 +110,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase => //--------------- when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){ - downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle) + downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.bits.tdata ).asTypeOf(new Header_Info_Bundle) } @@ -122,7 +124,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase => when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){ - downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata + downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.bits.tdata } //--------------- @@ -146,10 +148,10 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase => } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateIdle ){ isDownStreamError := true.B printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") - } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateIdle ){ + } .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateIdle ){ isDownStreamError := true.B printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") - } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateIdle ){ + } .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvSteteNext === DownRecvStateIdle ){ isDownStreamError := true.B printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){ @@ -215,7 +217,7 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase => assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) ) } -abstract ShinSlvPhyDownStream extends ShinSlvPhyBase +abstract class ShinSlvPhyDownStream extends ShinSlvPhyBase with ShinSlvPhyDownStreamRecv with ShinSlvPhyDownStreamSend{ @@ -507,7 +509,7 @@ class ShinSlvBase extends ShinSlvLinkBase with ShinSlvLinkInit with ShinSlvLinkBCast with ShinSlvLinkUCast{ - assert( VecInit(upRegMuxInit).contains((x:Bool) = > (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" ) + assert( VecInit(upRegMuxInit).count((x:Bool) => (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" ) }