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spi拉通

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This commit is contained in:
Ruige Lee
2025-05-13 11:32:38 +08:00
parent 51f941a8a6
commit a39a15e1d0
2 changed files with 12 additions and 12 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
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@@ -249,13 +249,13 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
for( i <- 0 until 8 ){
cReg.smEnqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) )
)
cReg.smDeqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) )
)
}