From a39a15e1d04540b0547189a35bf7f7f1da331cfd Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Tue, 13 May 2025 11:32:38 +0800
Subject: [PATCH] =?UTF-8?q?spi=E6=8B=89=E9=80=9A?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
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---
 src/main/scala/backBoard/shin/Interface.scala |  4 ++--
 .../scala/backBoard/shin/SpiInterface.scala   | 20 +++++++++----------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 9073f3a..123416d 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -249,13 +249,13 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   for( i <- 0 until 8 ){
     cReg.smEnqAddr(i) := 
       Cat(
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) ),
         RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) )
       )
     cReg.smDeqAddr(i) := 
       Cat(
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) ),
         RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) )
       )
   }
 
diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index d9121e4..a33a32f 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -70,9 +70,9 @@ class SpiInterface extends Module{
      
 //   spiRegUp.io.enw   := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
 
-    io.isEnR := isSckPosedge & ~shiftCSn(1+1) & bitSel === 7.U & byteSel >= 3.U & isSpiRead
-    io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
-    io.dataw := RegNext(exReg)
+    io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiRead  & byteSel >= 3.U 
+    io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiWrite & byteSel >= 3.U
+    io.dataw := exReg
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
     bitSel   := 0.U
@@ -86,12 +86,12 @@ class SpiInterface extends Module{
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     addrSel := 0.U
-  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
+  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
     addrSel := exReg
-  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
+  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
     addrSel := Cat(exReg, addrSel(7,0))
   } .otherwise{ // byteSel > 1.U
-    when( isSckPosedge & byteSel > 3.U & bitSel === 7.U ){
+    when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel === 7.U ){
       addrSel := addrSel + 1.U
     }
   }
@@ -99,14 +99,14 @@ class SpiInterface extends Module{
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     spiCmd  := "hFF".U
-  } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U ){ //CS为低，且SCK上跳的第0byte
-    spiCmd := Cat( spiCmd(6,0), shiftMOSI(1) )
+  } .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 7.U ){ //CS为低，且SCK上跳的第0byte
+    spiCmd := exReg
   }
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳 //第一个byte
     exReg := 0.U
-  } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
-    when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
+  } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 7.U ){ //CS为低，且SCK上跳补一拍 的第0bit
+    when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte
       exReg := 0.U
     } .otherwise{
       when( isSpiWrite ){