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spi拉通

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This commit is contained in:
Ruige Lee
2025-05-13 11:32:38 +08:00
parent 51f941a8a6
commit a39a15e1d0
2 changed files with 12 additions and 12 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -249,13 +249,13 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
for( i <- 0 until 8 ){
cReg.smEnqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) )
)
cReg.smDeqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) )
)
}

20
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -70,9 +70,9 @@ class SpiInterface extends Module{
// spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
io.isEnR := isSckPosedge & ~shiftCSn(1+1) & bitSel === 7.U & byteSel >= 3.U & isSpiRead
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := RegNext(exReg)
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiRead & byteSel >= 3.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiWrite & byteSel >= 3.U
io.dataw := exReg
when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
@@ -86,12 +86,12 @@ class SpiInterface extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrSel := exReg
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0))
} .otherwise{ // byteSel > 1.U
when( isSckPosedge & byteSel > 3.U & bitSel === 7.U ){
when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel === 7.U ){
addrSel := addrSel + 1.U
}
}
@@ -99,14 +99,14 @@ class SpiInterface extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := Cat( spiCmd(6,0), shiftMOSI(1) )
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 7.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := exReg
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 7.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte
exReg := 0.U
} .otherwise{
when( isSpiWrite ){