ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

改变读写操作方式，从单次跳变变为持续操作

Browse Source 
增加4号测试寄存器，实际地址为4<<1
This commit is contained in:
RuigeLee
2024-03-16 20:46:35 +08:00
parent 2b18de45e6
commit a29c01c812
2 changed files with 16 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -77,6 +77,7 @@ class BackBoardMstBase extends Module{ //10M
val slvNum = RegInit(0.U(6.W)) val slvNum = RegInit(0.U(6.W))
val slvOffLine = RegInit(0.U(6.W)) val slvOffLine = RegInit(0.U(6.W))
val testReg = RegInit("haa55".U(16.W))
lvdsMst.io.rst_n := ~reset.asBool lvdsMst.io.rst_n := ~reset.asBool
lvdsMst.io.reset_calib := io.reset_calib lvdsMst.io.reset_calib := io.reset_calib
@@ -135,17 +136,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val regOut = Wire(UInt(16.W)) val regOut = Wire(UInt(16.W))
val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B ) // val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B ) // val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
mirrorDown.io.enw := isAccessSRAM & ~fsmcCSWRSync(2) & fsmcCSWRSync(1) mirrorDown.io.enw := isAccessSRAM & fsmcCSSync(1) & fsmcWRSync(1) //~fsmcCSWRSync(2) & fsmcCSWRSync(1)
mirrorDown.io.addrw := activeAddr mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := io.FSMC.ADIn mirrorDown.io.dataw := io.FSMC.ADIn
mirrorUp.io.enr := isAccessSRAM & ~fsmcCSRDSync(2) & fsmcCSRDSync(1) mirrorUp.io.enr := isAccessSRAM & fsmcCSSync(1) & fsmcRDSync(1) // ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
mirrorUp.io.addrr := activeAddr mirrorUp.io.addrr := activeAddr
@@ -171,12 +172,13 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
), ),
( activeAddr === 2.U) -> slvNum, ( activeAddr === 2.U) -> slvNum,
( activeAddr === 3.U) -> slvOffLine, ( activeAddr === 3.U) -> slvOffLine,
( activeAddr === 4.U) -> testReg,
)) ))
when( isAccessReg & ~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){ when( isAccessReg & fsmcCSSync(1) & fsmcWRSync(1) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
isRegRefleshFlip := ~isRegRefleshFlip isRegRefleshFlip := ~isRegRefleshFlip
wrRegAddr := activeAddr wrRegAddr := activeAddr
@@ -210,8 +212,6 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
when( wrRegAddr === 1.U ){ when( wrRegAddr === 1.U ){
ctrlTransmit := wrRegData.extract(5) ctrlTransmit := wrRegData.extract(5)
ctrlSynch := wrRegData.extract(1) ctrlSynch := wrRegData.extract(1)
when( wrRegData.extract(0) ){ when( wrRegData.extract(0) ){
@@ -221,6 +221,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
} }
} }
when( wrRegAddr === 4.U ){
testReg := wrRegData
}
} }
} }

8
src/main/scala/backBoard/Readme.md
View File

@@ -5,10 +5,10 @@
* 数据地址线 AD 16比特位宽 * 数据地址线 AD 16比特位宽
* 地址锁存 ADV 正逻辑 * 地址锁存 ADVn 负逻辑
* 读使能 WR 正逻辑 * 读使能 RDn 负逻辑
* 写使能 WR 正逻辑 * 写使能 WRn 负逻辑
* 片选 CS 正逻辑 * 片选 CSn 负逻辑
使用要求：地址锁存时ADV保持高至少30ns， 写入时CS,WR保持高至少30ns，读出时CS,RD保持高至少30ns方可读取数据线上数据 使用要求：地址锁存时ADV保持高至少30ns， 写入时CS,WR保持高至少30ns，读出时CS,RD保持高至少30ns方可读取数据线上数据