From a29c01c812f59c8cc1cefea60147731bdc45808b Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Sat, 16 Mar 2024 20:46:35 +0800
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---
 src/main/scala/backBoard/BackBoardMst.scala | 19 ++++++++++++-------
 src/main/scala/backBoard/Readme.md          |  8 ++++----
 2 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 0e02ca8..f1d8f34 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -77,6 +77,7 @@ class BackBoardMstBase extends Module{ //10M
 
   val slvNum  = RegInit(0.U(6.W))
   val slvOffLine = RegInit(0.U(6.W))
+  val testReg = RegInit("haa55".U(16.W))
 
   lvdsMst.io.rst_n       := ~reset.asBool
   lvdsMst.io.reset_calib := io.reset_calib
@@ -135,17 +136,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     val regOut = Wire(UInt(16.W))
 
 
-    val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
-    val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
+    // val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
+    // val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
     
 
 
 
-    mirrorDown.io.enw    := isAccessSRAM & ~fsmcCSWRSync(2) & fsmcCSWRSync(1)
+    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(1) & fsmcWRSync(1) //~fsmcCSWRSync(2) & fsmcCSWRSync(1)
     mirrorDown.io.addrw  := activeAddr
     mirrorDown.io.dataw  := io.FSMC.ADIn
 
-    mirrorUp.io.enr    := isAccessSRAM & ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
+    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(1) & fsmcRDSync(1) // ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
     mirrorUp.io.addrr  := activeAddr
 
 
@@ -171,12 +172,13 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
         ),
       ( activeAddr === 2.U) -> slvNum,
       ( activeAddr === 3.U) -> slvOffLine,
+      ( activeAddr === 4.U) -> testReg,
     ))
 
 
   
 
-    when( isAccessReg & ~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
+    when( isAccessReg & fsmcCSSync(1) & fsmcWRSync(1) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
 
       isRegRefleshFlip := ~isRegRefleshFlip
       wrRegAddr        := activeAddr
@@ -210,8 +212,6 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     when( wrRegAddr === 1.U ){
       ctrlTransmit := wrRegData.extract(5)
 
-
-
       ctrlSynch    := wrRegData.extract(1)
 
       when( wrRegData.extract(0) ){
@@ -221,6 +221,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
       }
 
     }
+
+    when( wrRegAddr === 4.U ){
+      testReg := wrRegData
+    }
+
   }
 
 }
diff --git a/src/main/scala/backBoard/Readme.md b/src/main/scala/backBoard/Readme.md
index 9395349..23be57b 100644
--- a/src/main/scala/backBoard/Readme.md
+++ b/src/main/scala/backBoard/Readme.md
@@ -5,10 +5,10 @@
 
 * 数据地址线 AD 16比特位宽
 
-* 地址锁存 ADV 正逻辑
-* 读使能 WR  正逻辑
-* 写使能 WR 正逻辑
-* 片选   CS 正逻辑
+* 地址锁存 ADVn 负逻辑
+* 读使能 RDn  负逻辑
+* 写使能 WRn 负逻辑
+* 片选   CSn 负逻辑
 
 
 使用要求：地址锁存时ADV保持高至少30ns， 写入时CS,WR保持高至少30ns，读出时CS,RD保持高至少30ns方可读取数据线上数据