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RuigeLee
2025-09-11 14:11:40 +08:00
parent d46e06d5b0
commit a24abbc098
1 changed files with 20 additions and 0 deletions
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20
src/main/scala/backBoard/shin/Interface.scala
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@@ -482,12 +482,18 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
)}.reduce(_++_) ++
( 0 until 8 ).map{ i =>
( addr === ("h301".U(16.W) + (i*4).U) ) -> cReg.smUsedDepth(i)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h303".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(10,8)
} ++
( 0 until 4 ).map{ i =>
( addr === ("h400".U(16.W) + i.U) ) -> cReg.wdtStatus( 8*i+7, 8*i+0 )
} ++
( 0 until 4 ).map{ i =>
( addr === ("h404".U(16.W) + i.U) ) -> cReg.wdtEnable( 8*i+7, 8*i+0 )
} ++
(for( i <- 0 until 17; j <- 0 until 4 ) yield {
@@ -501,12 +507,26 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
) ++
( 0 until 8 ).map{ i =>
( addr === ("h508".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h510".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h518".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h520".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h528".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h530".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h538".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h540".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
} ++
Seq()