diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index b3718f0..8d3cec5 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -482,12 +482,18 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       )}.reduce(_++_) ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h301".U(16.W) + (i*4).U) )  -> cReg.smUsedDepth(i)
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h303".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
       } ++
 
       ( 0 until 4 ).map{ i =>
         ( addr === ("h400".U(16.W) + i.U) )  -> cReg.wdtStatus( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 4 ).map{ i =>
         ( addr === ("h404".U(16.W) + i.U) )  -> cReg.wdtEnable( 8*i+7, 8*i+0 )
       } ++
       (for( i <- 0 until 17; j <- 0 until 4 ) yield {
@@ -501,12 +507,26 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       ) ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h508".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h510".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h518".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h520".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h528".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h530".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h538".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
         ( addr === ("h540".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
       } ++
       Seq()