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调整busrate spisel encryptkey rpltimestamp的地址

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开放localDevIndex的spi读权限
txlength，smenq/deq的形式仍然需要讨论，未修改
This commit is contained in:
Ruige Lee
2025-05-16 20:17:02 +08:00
parent 5c729658d1
commit a0deb68fd6
3 changed files with 24 additions and 15 deletions
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32
src/main/scala/backBoard/shin/Interface.scala
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@@ -9,9 +9,9 @@ class CommonRegisterBundle extends Bundle{
val hwVersion = UInt(8.W)
val hwSerial = UInt(48.W)
val busRate = UInt(16.W)
val busRate = UInt(8.W)
val spiSel = UInt(2.W)
val spiSel = UInt(2.W)
// val isSoftReset = Bool()
val encryptKey = UInt(128.W)
@@ -96,6 +96,8 @@ class SlaveRegisterBundle extends Bundle{
// val dcSyncWidth = UInt(16.W)
val localDevIndex = UInt(16.W)
//链路寄存器组
// val isDevOnLeft = UInt(2.W)
val isDevOnLeftModify = Bool()
@@ -168,6 +170,8 @@ class InterfaceIO extends Bundle{
val mReg = Output(new MasterRegisterBundle)
val sReg = Output(new SlaveRegisterBundle)
val localDevIndex = Input(UInt(16.W))
// val isDevOnLeft = Input(UInt(2.W))
val isDevOnLeftModify = Input(Bool())
val indexOfLeftDev = Input(UInt(14.W))
@@ -238,8 +242,10 @@ abstract class InterfaceBase extends Module{
}) ++
Seq(
(addr === "h8".U ) -> cReg.busRate( 7,0),
(addr === "h9".U ) -> cReg.busRate(15,8),
(addr === "h8".U ) -> cReg.busRate( 7,0 ),
(addr === "h9".U ) -> cReg.spiSel,
(addr === "ha".U & isSlvMode) -> sReg.localDevIndex,
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h21".U & isMstMode) -> mReg.txLength,
@@ -247,14 +253,14 @@ abstract class InterfaceBase extends Module{
(addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
(addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
(addr === "h27".U ) -> cReg.spiSel
) ++
((0 until 16).map{ i =>
(addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
(addr === ("h50".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
}) ++
Seq(
@@ -434,21 +440,16 @@ trait InterfaceMCUop{ this: InterfaceBase =>
}.reverse
)
cReg.busRate :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ),
RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U )
)
cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U )
cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U )
cReg.encryptKey :=
Cat(
(0 until 16).map{ i =>
RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U )
RegEnable( dataw, 0.U, isEnW & addrSel === ("h50".U + i.U) & cReg.mstOrSlv === 0.U )
}.reverse
)
cReg.spiSel :=
RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h27".U & cReg.mstOrSlv === 0.U )
mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
@@ -727,6 +728,9 @@ with InterfaceSync
// io.smEnqAddr := cReg.smEnqAddr
// io.smDeqAddr := cReg.smDeqAddr
sReg.localDevIndex := io.localDevIndex
// sReg.isDevOnLeft := io.isDevOnLeft
sReg.isDevOnLeftModify := io.isDevOnLeftModify
sReg.indexOfLeftDev := io.indexOfLeftDev