From a0deb68fd69ea63351fdb5a3f1366037f6303b3b Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 16 May 2025 20:17:02 +0800 Subject: [PATCH] =?UTF-8?q?=E8=B0=83=E6=95=B4busrate=20spisel=20encryptkey?= =?UTF-8?q?=20rpltimestamp=E7=9A=84=E5=9C=B0=E5=9D=80=20=E5=BC=80=E6=94=BE?= =?UTF-8?q?localDevIndex=E7=9A=84spi=E8=AF=BB=E6=9D=83=E9=99=90=20txlength?= =?UTF-8?q?=EF=BC=8Csmenq/deq=E7=9A=84=E5=BD=A2=E5=BC=8F=E4=BB=8D=E7=84=B6?= =?UTF-8?q?=E9=9C=80=E8=A6=81=E8=AE=A8=E8=AE=BA=EF=BC=8C=E6=9C=AA=E4=BF=AE?= =?UTF-8?q?=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 32 +++++++++++-------- src/main/scala/backBoard/shin/ShinTop.scala | 2 ++ .../scala/backBoard/shin/SlaveParser.scala | 5 ++- 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index ed34754..7c3f613 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -9,9 +9,9 @@ class CommonRegisterBundle extends Bundle{ val hwVersion = UInt(8.W) val hwSerial = UInt(48.W) - val busRate = UInt(16.W) + val busRate = UInt(8.W) - val spiSel = UInt(2.W) + val spiSel = UInt(2.W) // val isSoftReset = Bool() val encryptKey = UInt(128.W) @@ -96,6 +96,8 @@ class SlaveRegisterBundle extends Bundle{ // val dcSyncWidth = UInt(16.W) + val localDevIndex = UInt(16.W) + //链路寄存器组 // val isDevOnLeft = UInt(2.W) val isDevOnLeftModify = Bool() @@ -168,6 +170,8 @@ class InterfaceIO extends Bundle{ val mReg = Output(new MasterRegisterBundle) val sReg = Output(new SlaveRegisterBundle) + val localDevIndex = Input(UInt(16.W)) + // val isDevOnLeft = Input(UInt(2.W)) val isDevOnLeftModify = Input(Bool()) val indexOfLeftDev = Input(UInt(14.W)) @@ -238,8 +242,10 @@ abstract class InterfaceBase extends Module{ }) ++ Seq( - (addr === "h8".U ) -> cReg.busRate( 7,0), - (addr === "h9".U ) -> cReg.busRate(15,8), + (addr === "h8".U ) -> cReg.busRate( 7,0 ), + (addr === "h9".U ) -> cReg.spiSel, + (addr === "ha".U & isSlvMode) -> sReg.localDevIndex, + (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), (addr === "h21".U & isMstMode) -> mReg.txLength, @@ -247,14 +253,14 @@ abstract class InterfaceBase extends Module{ (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0), (addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8), - (addr === "h27".U ) -> cReg.spiSel + ) ++ ((0 until 16).map{ i => - (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 ) + (addr === ("h50".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 ) }) ++ Seq( @@ -434,21 +440,16 @@ trait InterfaceMCUop{ this: InterfaceBase => }.reverse ) - cReg.busRate := - Cat( - RegEnable( dataw, 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ), - RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U ) - ) + cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U ) + cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ) cReg.encryptKey := Cat( (0 until 16).map{ i => - RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U ) + RegEnable( dataw, 0.U, isEnW & addrSel === ("h50".U + i.U) & cReg.mstOrSlv === 0.U ) }.reverse ) - cReg.spiSel := - RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h27".U & cReg.mstOrSlv === 0.U ) mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U ) @@ -727,6 +728,9 @@ with InterfaceSync // io.smEnqAddr := cReg.smEnqAddr // io.smDeqAddr := cReg.smDeqAddr + + sReg.localDevIndex := io.localDevIndex + // sReg.isDevOnLeft := io.isDevOnLeft sReg.isDevOnLeftModify := io.isDevOnLeftModify sReg.indexOfLeftDev := io.indexOfLeftDev diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 6b656f5..317ff0f 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -347,6 +347,8 @@ trait ShinTopSlave{ this: ShinTopBase => interface.io.lvds <> slaveParser.io.lvds + interface.io.localDevIndex := slaveParser.io.localDevIndex + //从站链路寄存器 // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 74a3cb6..4aeeb04 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -46,6 +46,9 @@ class SlaveParserIO extends Bundle{ val trigAddr = Input( Vec(8, UInt(15.W)) ) + + val localDevIndex = Output(UInt(16.W)) + //开放链路寄存器组给interface // val isDevOnLeft = Output(UInt(2.W)) val isDevOnLeftModify = Output(Bool()) @@ -103,7 +106,7 @@ abstract class SlaveParserBase extends Module{ // val isDeviceModified: Bool = RegInit(true.B) - val localDevIndex = RegInit(0.U(14.W)) //当前设备索引 + val localDevIndex = RegInit(0.U(14.W)); io.localDevIndex := localDevIndex //当前设备索引 // dontTouch(localDevIndex)