over sample in spi

src/main/scala/backBoard/BackBoardMst.scala

@@ -17,14 +17,13 @@ class BackBoardMstIO extends Bundle{
 
   val clk4            = Input( Bool() )
 
-  val reset = Input(Bool())
 }
 
 
-class BackBoardMst extends RawModule{
+class BackBoardMst extends Module{
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
-  withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
+
     val spi = Module( new SpiSlv )
     val in  = Module( new CDR4MultiIn )
     val out = Module( new CDROutBus )
@@ -32,25 +31,21 @@ class BackBoardMst extends RawModule{
     spi.io.CS   := io.CS
     io.MISO     := spi.io.MISO
     spi.io.MOSI := io.MOSI
+    spi.io.SCK := io.SCK
 
-    io.interrupt := spi.io.interrupt
+    // io.interrupt := spi.io.interrupt
+    io.interrupt := false.B
 
     spi.io.CDRIn  <> in.io.latDat
     spi.io.CDROut <> out.io.pkgDat
 
     in.io.clk4 := io.clk4
+    spi.io.clk4 := io.clk4
 
     in.io.dat  := io.downStreamReqDat
     io.downStreamRespdat := out.io.dat
 
-    spi.clock := io.SCK.asClock
-    in.clock  := io.SCK.asClock
-    out.clock := io.SCK.asClock
 
-    spi.reset := io.reset.asAsyncReset
-    in.reset  := io.reset.asAsyncReset
-    out.reset := io.reset.asAsyncReset
-  }
 }
 
 

src/main/scala/backBoard/SpiSlv.scala

@@ -12,46 +12,63 @@ class SpiSlvIO extends Bundle{
   val CS   = Input(Bool())
   val MISO = Output(Bool())
   val MOSI = Input(Bool())
+  val SCK  = Input(Bool())
+
+  val clk4 = Input(Bool())
 
   val CDRIn  = Flipped(Decoupled(new CDRData))
   val CDROut = Decoupled(new CDRData)
 
-  val interrupt = Output(Bool())
-
-
 }
 
-class SpiSlv extends Module with RequireAsyncReset{
+class SpiSlv extends Module{
   val io: SpiSlvIO = IO(new SpiSlvIO)
 
-  // val spiTrans  = Reg( new CDR_Master_Interface_Bundle )
-  val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle))
+  val CDROutValidSet      = Wire(Bool())
+  val CDROutValidSetAsync = ShiftRegister(CDROutValidSet, 2, false.B, true.B)
+  val CDROutValidReset    = RegNext(CDROutValidSetAsync, false.B)
 
-  io.CDRIn.ready := io.CS
-  io.interrupt   := false.B
-  io.MISO := RegNext(centReg.asUInt.extract( 6+8+32+2+16-1 ))
+  // val CDRInValidSet = RegInit(false.B)
+  val CDRInValidReset = Wire(Bool())
+  val CDRInValidResetAsync = ShiftRegister( CDRInValidReset, 2, false.B, true.B)
 
-  when( ~io.CS ){
-    
-    centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
-  } .otherwise{
+  val cent = Wire(new CDR_Master_Interface_Bundle)
+  withClockAndReset( io.clk4.asClock, reset ){
+    val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg
+    val sckShift = ShiftRegisters( io.SCK, 4, false.B, true.B )
+    val csShift  = ShiftRegisters( io.CS, 4, true.B, true.B )
 
-    when( io.CDROut.fire ){
-      centReg.op := OPBUSY
+
+    val CDROutValidSetReg        = RegInit(false.B); CDROutValidSet := CDROutValidSetReg
+    val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B )
+
+    val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B )
+    val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(3) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg
+
+    when( CDROutValidSetReg & CDROutValidResetAsync ){
+      CDROutValidSetReg := false.B
+      centReg.op := 1.U
+    } .elsewhen( ~csShift(3) & csShift(2) ){
+      CDROutValidSetReg := true.B
     }
-    when( io.CDRIn.valid ){
-      when( centReg.op === OPBUSY & centReg.address === io.CDRIn.bits.address ){
+
+    io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
+
+    val sckPosedge = ~sckShift(3) & sckShift(2)
+    val sckNegedge = sckShift(3) & ~sckShift(2)
+
+    when( ~csShift(3) ){
+      when( sckNegedge ){
+        centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
+      }
+    } .otherwise{
+      when( CDRInValidSetAsync & ~CDROutValidSetReg ){
         centReg.address  := io.CDRIn.bits.address
         centReg.register := io.CDRIn.bits.register
         centReg.data     := io.CDRIn.bits.data
-        centReg.hash     := 0.U
-        centReg.op       := OPIDLE        
-      } .otherwise{
-        io.interrupt := true.B
+        centReg.op       := 0.U
       }
-
     }
-
   }
 
   val CDROutValid = RegInit(false.B); io.CDROut.valid := CDROutValid
@@ -59,26 +76,12 @@ class SpiSlv extends Module with RequireAsyncReset{
 
   when( io.CDROut.fire ){
     CDROutValid := false.B
-  } .elsewhen( io.CS & centReg.op === OPMSTT & ~CDROutValid ){
+  } .elsewhen( CDROutValidSet & ~CDROutValidSetAsync ){
     CDROutValid := true.B
-
-
-
-    CDROutInfo.address  := centReg.address
-    CDROutInfo.register := centReg.register
-    CDROutInfo.data     := centReg.data
-    CDROutInfo.hash     := 0.U
+    CDROutInfo  := cent
   }
 
-
-
-
-  def OPIDLE = 0.U
-  def OPMSTT = 1.U
-  // def OPSLVT = 2.U
-  def OPBUSY = 3.U
-
-
+  io.CDRIn.ready := CDRInValidResetAsync
 
 }
 

src/test/scala/gcd/BackPlaneMstTest.scala

@@ -28,12 +28,11 @@ class BackPlaneMstTest extends RawModule{
     // dut.io.CS   := io.CS
     // io.MISO     := dut.io.MISO
     // dut.io.MOSI := io.MOSI
-    dut.io.SCK  := ~io.SCK
+    dut.io.SCK  := io.SCK
 
     dut.io.clk4 := io.clk4
     io.interrupt := dut.io.interrupt
 
-    dut.io.reset := io.reset
 
     io.req.ready := true.B
     val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat