89 lines
2.6 KiB
Scala
89 lines
2.6 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class CDR_Master_Interface_Bundle extends CDRData{
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val op = UInt(2.W)
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}
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class SpiSlvIO extends Bundle{
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val CS = Input(Bool())
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val MISO = Output(Bool())
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val MOSI = Input(Bool())
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val SCK = Input(Bool())
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val clk4 = Input(Bool())
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val CDRIn = Flipped(Decoupled(new CDRData))
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val CDROut = Decoupled(new CDRData)
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}
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class SpiSlv extends Module{
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val io: SpiSlvIO = IO(new SpiSlvIO)
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val CDROutValidSet = Wire(Bool())
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val CDROutValidSetAsync = ShiftRegister(CDROutValidSet, 2, false.B, true.B)
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val CDROutValidReset = RegNext(CDROutValidSetAsync, false.B)
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// val CDRInValidSet = RegInit(false.B)
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val CDRInValidReset = Wire(Bool())
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val CDRInValidResetAsync = ShiftRegister( CDRInValidReset, 2, false.B, true.B)
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val cent = Wire(new CDR_Master_Interface_Bundle)
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withClockAndReset( io.clk4.asClock, reset ){
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val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg
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val sckShift = ShiftRegisters( io.SCK, 4, false.B, true.B )
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val csShift = ShiftRegisters( io.CS, 4, true.B, true.B )
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val CDROutValidSetReg = RegInit(false.B); CDROutValidSet := CDROutValidSetReg
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val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B )
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val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B )
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val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(3) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg
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when( CDROutValidSetReg & CDROutValidResetAsync ){
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CDROutValidSetReg := false.B
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centReg.op := 1.U
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} .elsewhen( ~csShift(3) & csShift(2) ){
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CDROutValidSetReg := true.B
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}
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io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
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val sckPosedge = ~sckShift(3) & sckShift(2)
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val sckNegedge = sckShift(3) & ~sckShift(2)
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when( ~csShift(3) ){
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when( sckNegedge ){
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centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
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}
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} .otherwise{
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when( CDRInValidSetAsync & ~CDROutValidSetReg ){
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centReg.address := io.CDRIn.bits.address
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centReg.register := io.CDRIn.bits.register
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centReg.data := io.CDRIn.bits.data
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centReg.op := 0.U
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}
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}
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}
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val CDROutValid = RegInit(false.B); io.CDROut.valid := CDROutValid
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val CDROutInfo = Reg(new CDRData); io.CDROut.bits := CDROutInfo
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when( io.CDROut.fire ){
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CDROutValid := false.B
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} .elsewhen( CDROutValidSet & ~CDROutValidSetAsync ){
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CDROutValid := true.B
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CDROutInfo := cent
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}
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io.CDRIn.ready := CDRInValidResetAsync
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}
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