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Revert "改命令"

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This reverts commit ea7ef3c9f9.
This commit is contained in:
Ruige Lee
2025-08-28 13:05:37 +08:00
parent ea7ef3c9f9
commit a0320e1993
1 changed files with 11 additions and 23 deletions
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34
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -44,7 +44,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1) val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B) val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
val isSckNegedge = ShiftRegister(isSckPosedge, 3, false.B, true.B) //shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上 val isSckNegedge = shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上
val exRego = Reg(UInt(8.W)) val exRego = Reg(UInt(8.W))
val exRegi = Reg(UInt(8.W)) val exRegi = Reg(UInt(8.W))
@@ -53,7 +53,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val addrw = RegInit(0.U(16.W)) val addrw = RegInit(0.U(16.W))
val addrr = RegInit(0.U(16.W)) val addrr = RegInit(0.U(16.W))
val spiCmd = Reg(UInt(1.W)) val spiCmd = Reg(UInt(8.W))
val isSpiWrite = spiCmd === 0.U val isSpiWrite = spiCmd === 0.U
val isSpiRead = spiCmd === 1.U val isSpiRead = spiCmd === 1.U
@@ -62,11 +62,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val byteSel = Reg(UInt(12.W)) val byteSel = Reg(UInt(12.W))
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exRegi === 1.U & byteSel === 3.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U)
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exRegi io.dataw := exRegi
io.addrr := addrr io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
io.addrw := addrw io.addrw := addrw
// io.addrSel := // io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况 // Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
@@ -107,7 +108,11 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
} }
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := exRegi
}
@@ -120,15 +125,6 @@ class SSpiInterface extends SpiInterfaceBase{
sck := spi.sck sck := spi.sck
csn := spi.csn csn := spi.csn
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & spi.miso === 1.U & byteSel === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := spi.miso
}
spi.miso := exRego.extract(7) spi.miso := exRego.extract(7)
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -172,14 +168,6 @@ class QSpiInterface extends SpiInterfaceBase{
qspi.miso := exRego(7, 4) qspi.miso := exRego(7, 4)
qspi.isDirIn := ~isSpiRead qspi.isDirIn := ~isSpiRead
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & qspi.miso === "b1000".U & byteSel === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := qspi.miso.extract(3)
}
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U bitSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){