From a0320e199313cf910a37eeb87118a6124f8725fe Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 28 Aug 2025 13:05:37 +0800
Subject: [PATCH] =?UTF-8?q?Revert=20"=E6=94=B9=E5=91=BD=E4=BB=A4"?=
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This reverts commit ea7ef3c9f9eeddf4fab8bcae6c06eea58d0e2bef.
---
 .../scala/backBoard/shin/SpiInterface.scala   | 34 ++++++-------------
 1 file changed, 11 insertions(+), 23 deletions(-)

diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 3d93425..c8e6b96 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -44,7 +44,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val isSckPosedge     = ~shiftSCK(2) & shiftSCK(1)
   val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
 
-  val isSckNegedge     =  ShiftRegister(isSckPosedge, 3, false.B, true.B) //shiftSCK(2) & ~shiftSCK(1)  //确定下降沿放数据到数据线上
+  val isSckNegedge     =  shiftSCK(2) & ~shiftSCK(1)  //确定下降沿放数据到数据线上
 
   val exRego = Reg(UInt(8.W))
   val exRegi = Reg(UInt(8.W))
@@ -53,7 +53,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
 
   val addrw = RegInit(0.U(16.W))
   val addrr = RegInit(0.U(16.W))
-  val spiCmd  = Reg(UInt(1.W))
+  val spiCmd  = Reg(UInt(8.W))
 
   val isSpiWrite = spiCmd === 0.U
   val isSpiRead  = spiCmd === 1.U
@@ -62,11 +62,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val byteSel = Reg(UInt(12.W))
 
 
-
-
+  io.isEnR := 
+             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exRegi === 1.U & byteSel === 3.U ) |
+             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead  & byteSel >= 4.U)
   io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
   io.dataw := exRegi
-  io.addrr := addrr
+  io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
   io.addrw := addrw
   // io.addrSel :=
   //   Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
@@ -107,7 +108,11 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
     }
   }
 
-
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    spiCmd  := "hFF".U
+  } .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
+    spiCmd := exRegi
+  }
 
 
 
@@ -120,15 +125,6 @@ class SSpiInterface extends SpiInterfaceBase{
   sck     := spi.sck
   csn     := spi.csn
 
-  io.isEnR := 
-             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & spi.miso === 1.U & byteSel === 2.U ) |
-             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
-
-  when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
-    spiCmd := spi.miso
-  }
-
-
   spi.miso := exRego.extract(7)
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -172,14 +168,6 @@ class QSpiInterface extends SpiInterfaceBase{
   qspi.miso := exRego(7, 4)
   qspi.isDirIn := ~isSpiRead
 
-  io.isEnR := 
-             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & qspi.miso === "b1000".U & byteSel === 2.U ) |
-             (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
-
-  when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
-    spiCmd := qspi.miso.extract(3)
-  }
-
   when( shiftCSn(2) & ~shiftCSn(1) ){
     bitSel := 0.U
   } .elsewhen( isSckPosedge & ~shiftCSn(1)  ){