bug payload 12bits

总线握手条件

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -92,7 +92,12 @@ trait CDRInAxis{ this: CDRInBase =>
 
   val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
 
-                val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER )
+  val payloadLen = Reg(UInt(12.W))
+  when( byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){
+    payloadLen := Cat( shiftData, 0.U(4.W) )
+  } .elsewhen( byteCnt === 1.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){
+    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
+  }
   
   val isArbLock: Bool
 

src/main/scala/backBoard/pico/BackSystem.scala

@@ -155,8 +155,8 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
 
 
   sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U
-  cdr.io.mem.valid  := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr
-  gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
+  cdr.io.mem.valid  := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr
+  gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
 
   pico.io.mem.ready := 
     Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready, 

tb/sw/src/SlvMain.c

@@ -139,7 +139,7 @@ void main()
 
 
 
-
+			*cdr_softReset = 1; //复位脉冲
 			*cdr_direct = 1; //方向转换
 
 			if(!isLast){