From 9fa54072f477b5a40008eb8c026baca1a24ecad2 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Mon, 4 Nov 2024 14:39:26 +0800 Subject: [PATCH] =?UTF-8?q?bug=20payload=2012bits=20=E6=80=BB=E7=BA=BF?= =?UTF-8?q?=E6=8F=A1=E6=89=8B=E6=9D=A1=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 9 +++++++-- src/main/scala/backBoard/pico/BackSystem.scala | 4 ++-- tb/sw/src/SlvMain.c | 2 +- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 2989623..832a11c 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -92,8 +92,13 @@ trait CDRInAxis{ this: CDRInBase => val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat) - val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ) - + val payloadLen = Reg(UInt(12.W)) + when( byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){ + payloadLen := Cat( shiftData, 0.U(4.W) ) + } .elsewhen( byteCnt === 1.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){ + payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ) + } + val isArbLock: Bool stateNext := diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index 33310c9..3c34ab3 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -155,8 +155,8 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U - cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr - gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr + cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr + gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr pico.io.mem.ready := Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready, diff --git a/tb/sw/src/SlvMain.c b/tb/sw/src/SlvMain.c index 3e266ad..7f086f6 100644 --- a/tb/sw/src/SlvMain.c +++ b/tb/sw/src/SlvMain.c @@ -139,7 +139,7 @@ void main() - + *cdr_softReset = 1; //复位脉冲 *cdr_direct = 1; //方向转换 if(!isLast){