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bug payload 12bits

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RuigeLee
2024-11-04 14:39:26 +08:00
parent 983f9e771d
commit 9fa54072f4
3 changed files with 10 additions and 5 deletions
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4
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -155,8 +155,8 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
pico.io.mem.ready :=
Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready,