bug payload 12bits

总线握手条件

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -92,8 +92,13 @@ trait CDRInAxis{ this: CDRInBase =>
 
   val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
 
-                val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER )
-
+  val payloadLen = Reg(UInt(12.W))
+  when( byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){
+    payloadLen := Cat( shiftData, 0.U(4.W) )
+  } .elsewhen( byteCnt === 1.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){
+    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
+  }
+  
   val isArbLock: Bool
 
   stateNext :=