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修改芯片码

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This commit is contained in:
RuigeLee
2024-05-11 17:21:05 +08:00
parent b264f729b4
commit 9c56c611e2
4 changed files with 20 additions and 20 deletions
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34
src/main/scala/backBoard/LocalRegisters.scala
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@@ -8,7 +8,7 @@ class ManualParamBundle extends Bundle{
val moduleID = UInt( 16.W ) val moduleID = UInt( 16.W )
val hwVersion = UInt( 16.W ) val hwVersion = UInt( 16.W )
val swVersion = UInt( 16.W ) val swVersion = UInt( 16.W )
val batchID = UInt( 16.W ) // val batchID = UInt( 16.W )
val serial = UInt( 48.W ) val serial = UInt( 48.W )
} }
@@ -38,27 +38,27 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
upReg(4) := 0.U upReg(4) := 0.U
upReg(5) := 0.U upReg(5) := 0.U
upReg(16) := param.vendorID(7,0) upReg(6) := param.vendorID(7,0)
upReg(17) := param.vendorID(15,8) upReg(7) := param.vendorID(15,8)
upReg(18) := param.moduleID(7,0) upReg(8) := param.moduleID(7,0)
upReg(19) := param.moduleID(15,8) upReg(9) := param.moduleID(15,8)
upReg(20) := param.hwVersion(7,0) upReg(10) := param.hwVersion(7,0)
upReg(21) := param.hwVersion(15,8) upReg(11) := param.hwVersion(15,8)
upReg(22) := param.swVersion(7,0) upReg(12) := param.swVersion(7,0)
upReg(23) := param.swVersion(15,8) upReg(13) := param.swVersion(15,8)
upReg(24) := param.batchID(7,0) // upReg(15) := param.batchID(7,0)
upReg(25) := param.batchID(15,8) // upReg(16) := param.batchID(15,8)
upReg(26) := param.serial(7,0) upReg(14) := param.serial(7,0)
upReg(27) := param.serial(15,8) upReg(15) := param.serial(15,8)
upReg(28) := param.serial(23,16) upReg(16) := param.serial(23,16)
upReg(29) := param.serial(31,24) upReg(17) := param.serial(31,24)
upReg(30) := param.serial(39,32) upReg(18) := param.serial(39,32)
upReg(31) := param.serial(47,40) upReg(19) := param.serial(47,40)
} }

2
src/main/verilog/defineParam.v
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@@ -2,5 +2,5 @@
`define MODULEID 16'h3344 `define MODULEID 16'h3344
`define HWVERSION 16'h5566 `define HWVERSION 16'h5566
`define SWVERSION 16'h7788 `define SWVERSION 16'h7788
`define BATCHID 16'h99aa // `define BATCHID 16'h99aa
`define SERIAL 48'hbbccddeeff00 `define SERIAL 48'hbbccddeeff00

2
src/main/verilog/di16_top.v
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@@ -152,7 +152,7 @@ DIn16 i_din16(
.param_moduleID(`MODULEID), .param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION), .param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION), .param_swVersion(`SWVERSION),
.param_batchID(`BATCHID), // .param_batchID(`BATCHID),
.param_serial(`SERIAL), .param_serial(`SERIAL),
.LED_PR(LED_PR), .LED_PR(LED_PR),
.in(in) .in(in)

2
src/main/verilog/do16_top.v
View File

@@ -156,7 +156,7 @@ DOut16 i_dout16(
.param_moduleID(`MODULEID), .param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION), .param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION), .param_swVersion(`SWVERSION),
.param_batchID(`BATCHID), // .param_batchID(`BATCHID),
.param_serial(`SERIAL), .param_serial(`SERIAL),
.LED_PR(LED_PR), .LED_PR(LED_PR),
.out(out), .out(out),