diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index cfcc6ed..34d5ee0 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -8,7 +8,7 @@ class ManualParamBundle extends Bundle{
   val moduleID = UInt( 16.W )
   val hwVersion = UInt( 16.W )
   val swVersion = UInt( 16.W )
-  val batchID  = UInt( 16.W )
+  // val batchID  = UInt( 16.W )
   val serial   = UInt( 48.W )
 }
 
@@ -38,27 +38,27 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
     upReg(4) := 0.U
     upReg(5) := 0.U
 
-    upReg(16) := param.vendorID(7,0)
-    upReg(17) := param.vendorID(15,8)
+    upReg(6) := param.vendorID(7,0)
+    upReg(7) := param.vendorID(15,8)
 
-    upReg(18) := param.moduleID(7,0)
-    upReg(19) := param.moduleID(15,8)
+    upReg(8) := param.moduleID(7,0)
+    upReg(9) := param.moduleID(15,8)
 
-    upReg(20) := param.hwVersion(7,0)
-    upReg(21) := param.hwVersion(15,8)
+    upReg(10) := param.hwVersion(7,0)
+    upReg(11) := param.hwVersion(15,8)
 
-    upReg(22) := param.swVersion(7,0)
-    upReg(23) := param.swVersion(15,8)
+    upReg(12) := param.swVersion(7,0)
+    upReg(13) := param.swVersion(15,8)
 
-    upReg(24) := param.batchID(7,0)
-    upReg(25) := param.batchID(15,8)
+    // upReg(15) := param.batchID(7,0)
+    // upReg(16) := param.batchID(15,8)
 
-    upReg(26) := param.serial(7,0)
-    upReg(27) := param.serial(15,8)
-    upReg(28) := param.serial(23,16)
-    upReg(29) := param.serial(31,24)
-    upReg(30) := param.serial(39,32)
-    upReg(31) := param.serial(47,40)    
+    upReg(14) := param.serial(7,0)
+    upReg(15) := param.serial(15,8)
+    upReg(16) := param.serial(23,16)
+    upReg(17) := param.serial(31,24)
+    upReg(18) := param.serial(39,32)
+    upReg(19) := param.serial(47,40)    
   }
 
 
diff --git a/src/main/verilog/defineParam.v b/src/main/verilog/defineParam.v
index eb03c9e..6670af1 100644
--- a/src/main/verilog/defineParam.v
+++ b/src/main/verilog/defineParam.v
@@ -2,5 +2,5 @@
 `define MODULEID  16'h3344
 `define HWVERSION 16'h5566
 `define SWVERSION 16'h7788
-`define BATCHID   16'h99aa
+// `define BATCHID   16'h99aa
 `define SERIAL    48'hbbccddeeff00
\ No newline at end of file
diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v
index 2283c80..3e9887c 100644
--- a/src/main/verilog/di16_top.v
+++ b/src/main/verilog/di16_top.v
@@ -152,7 +152,7 @@ DIn16 i_din16(
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
   .param_swVersion(`SWVERSION),
-  .param_batchID(`BATCHID),
+  // .param_batchID(`BATCHID),
   .param_serial(`SERIAL),
   .LED_PR(LED_PR),
   .in(in)
diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v
index 578ef34..dabf37d 100644
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -156,7 +156,7 @@ DOut16 i_dout16(
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
   .param_swVersion(`SWVERSION),
-  .param_batchID(`BATCHID),
+  // .param_batchID(`BATCHID),
   .param_serial(`SERIAL),
   .LED_PR(LED_PR),
   .out(out),