修改芯片码

2024-05-11 17:21:05 +08:00
parent b264f729b4
commit 9c56c611e2
4 changed files with 20 additions and 20 deletions
--- a/src/main/verilog/defineParam.v
+++ b/src/main/verilog/defineParam.v
@@ -2,5 +2,5 @@
 `define MODULEID  16'h3344
 `define HWVERSION 16'h5566
 `define SWVERSION 16'h7788
-`define BATCHID   16'h99aa
+// `define BATCHID   16'h99aa
 `define SERIAL    48'hbbccddeeff00