修改芯片码

2024-05-11 17:21:05 +08:00
parent b264f729b4
commit 9c56c611e2
4 changed files with 20 additions and 20 deletions
--- a/src/main/verilog/defineParam.v
+++ b/src/main/verilog/defineParam.v
@@ -2,5 +2,5 @@
 `define MODULEID  16'h3344
 `define HWVERSION 16'h5566
 `define SWVERSION 16'h7788
-`define BATCHID   16'h99aa
+// `define BATCHID   16'h99aa
 `define SERIAL    48'hbbccddeeff00
--- a/src/main/verilog/di16_top.v
+++ b/src/main/verilog/di16_top.v
@@ -152,7 +152,7 @@ DIn16 i_din16(
  .param_moduleID(`MODULEID),
  .param_hwVersion(`HWVERSION),
  .param_swVersion(`SWVERSION),
-  .param_batchID(`BATCHID),
+  // .param_batchID(`BATCHID),
  .param_serial(`SERIAL),
  .LED_PR(LED_PR),
  .in(in)
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -156,7 +156,7 @@ DOut16 i_dout16(
  .param_moduleID(`MODULEID),
  .param_hwVersion(`HWVERSION),
  .param_swVersion(`SWVERSION),
-  .param_batchID(`BATCHID),
+  // .param_batchID(`BATCHID),
  .param_serial(`SERIAL),
  .LED_PR(LED_PR),
  .out(out),