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为多相位模拟增加命令行,增加8b10b切换的测试

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This commit is contained in:
bacon
2025-09-08 16:47:30 +08:00
parent a63e14e6f6
commit 9c43daf51e
8 changed files with 155 additions and 41 deletions
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8
Makefile
View File

@@ -41,7 +41,7 @@ shin:
sbt "test:runMain test.testShinModule"
testShin:
./tb/shinTest/gen_pkt.py
python3 ./tb/shinTest/gen_pkt.py
mkdir -p generated/log
rm -rf generated/log/*
iverilog -Wall \
@@ -52,10 +52,10 @@ testShin:
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb.v
vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
./tb/shinTest/check_testcase.py
python3 ./tb/shinTest/check_testcase.py
testShinClk:
./tb/shinTest/gen_pkt_clk.py
python3 ./tb/shinTest/gen_pkt_clk.py --dev1 0 200
mkdir -p generated/log
rm -rf generated/log/*
iverilog -Wall \
@@ -66,7 +66,7 @@ testShinClk:
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb_clk.v
vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
./tb/shinTest/check_testcase.py
python3 ./tb/shinTest/check_testcase.py
testCDR:
iverilog -Wall \

26
tb/shinTest/Makefile_vcs
View File

@@ -24,12 +24,32 @@ testShin_vcs:
testShinClk_vcs:
python3 ./shinTest/gen_pkt_clk.py
python3 ./shinTest/gen_pkt_clk.py --dev1 0 90 --dev2 0 -90
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data1.txt
mv generated/wave.vcd generated/wave1.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 45 180 --dev3 25 -180
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data2.txt
mv generated/wave.vcd generated/wave2.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 45 190 --dev3 25 -190
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data3.txt
mv generated/wave.vcd generated/wave3.vcd
testShinMany_vcs:
@@ -58,7 +78,7 @@ testShin:
./shinTest/check_testcase.py
testShinClk:
./shinTest/gen_pkt_clk.py
./shinTest/gen_pkt_clk.py --dev1 0 200
mkdir -p generated/log
rm -rf generated/log/*
iverilog -Wall \
@@ -77,4 +97,4 @@ fstShinClk:
gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
clean:
rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.*
rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.*

2
tb/shinTest/ShinTopSpiTb.v
View File

@@ -442,7 +442,7 @@ begin
`ifdef VCS_COMPILE
$dumpfile("./generated/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称
//$dumpvars(0, ShinTopSpiTb);//tb模块名称
$dumpvars(0, ShinTopSpiTb.s_ShinTop_Mst);//tb模块名称
//$dumpvars(0, ShinTopSpiTb.s_ShinTop_slv124);//tb模块名称
//$dumpvars(0, ShinTopSpiTb.s_ShinTop_slv125);//tb模块名称

13
tb/shinTest/ShinTopSpiTb_clk.v
View File

@@ -12,13 +12,6 @@ module ShinTopSpiTb(
reg [15:0] multiCLK;
reg clock2;
reg [15:0] multiCLK2;
reg clock3;
reg [15:0] multiCLK3;
`include "dev_predef.vh"
`ifdef DEFINE_SLAVE_DEVICE
@@ -361,7 +354,6 @@ ShinTop s_ShinTop_slv3(
initial begin
clock = 0;
clock2 = 0;
reset = 1;
latch0 = 0;
@@ -407,6 +399,8 @@ generate
end
endgenerate
/*
//如果频率差到 80ppm，参数是： 8000640/1000080/8000640 [pass]
//如果频率差到120ppm，参数是： 8000960/1000120/8000960 [pass]
//如果频率差到160ppm，参数是： 8001280/1000160/8001280 [pass]
@@ -466,8 +460,11 @@ generate
end
end
endgenerate
*/
`include "slave_dev_clk.vh"
initial
begin
spidata_file = $fopen("spi_trans_data.txt", "w");

29
tb/shinTest/gen_pkt_clk.py
View File

@@ -2,11 +2,40 @@
#encoding=utf-8
from pyutils import *
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac
import argparse
if __name__ == '__main__':
parser = argparse.ArgumentParser()
# 可选参数
parser.add_argument("-d1", "--dev1", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
parser.add_argument("-d2", "--dev2", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
parser.add_argument("-d3", "--dev3", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
parser.add_argument("-d4", "--dev4", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
# 解析参数
args = parser.parse_args()
# 使用参数
dev_clk_info = dict()
if args.dev1 != [0, 0]:
dev_clk_info[1] = args.dev1
if args.dev2 != [0, 0]:
dev_clk_info[2] = args.dev2
if args.dev3 != [0, 0]:
dev_clk_info[3] = args.dev3
if args.dev4 != [0, 0]:
dev_clk_info[4] = args.dev4
environment.set_dev_clk(dev_clk_info)
environment.gen_slv_dev_for_clk(4)
environment.bringup()
rwregs.tc1()
#add_tc_2_runlist(errorPkt.tc1())
#add_tc_2_runlist(errorPkt.tc2())
#add_tc_2_runlist(errorPkt.tc3())

10
tb/shinTest/testcase/base.py
View File

@@ -2337,9 +2337,13 @@ def tc28():
+genIFRwDataCode(0, 0x74, False, 4)
+genIFRwDataCode(4, 0x74, False, 4)
+genMessageCode("--读取中断使能")
+genIFRwDataCode(0, 0x70, False, 4)
+genIFRwDataCode(4, 0x70, False, 4)
+genMessageCode("--配置中断")
#+genIFRwDataCode(0, 0x70, False, 4)
#+genIFRwDataCode(4, 0x70, False, 4)
+genIFRwDataCode(0, 0x70, True, 4, [0x03, 0x00, 0x00, 0xf0])
+genIFRwDataCode(4, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
+genIFRwDataCode(0, 0x7c, True, 2, [0x10, 0x80])
+genIFRwDataCode(4, 0x7c, True, 2, [0x10, 0x80])
+genMessageCode("--配置主从站")
+genIFRwDataCode(0, 0x00, True, 1, [0x01, ])

71
tb/shinTest/testcase/environment.py
View File

@@ -2,6 +2,9 @@ from pyutils import *
global_dev_num = 4
global_setting_dev_clk = dict()
def bringup():
gen_file_def = "sys_bringup"
@@ -177,7 +180,8 @@ def bringup():
add_tc_2_runlist(gen_file_def)
def __GenDevice(id, TerminateNode = False, diffclk = False):
def __GenDevice(id, TerminateNode = False):
global global_setting_dev_clk
dout_code = "dDat_w[%d]"%(id + 1, )
din_code = "uDat_w[%d]"%(id + 1, )
if TerminateNode:
@@ -186,9 +190,13 @@ def __GenDevice(id, TerminateNode = False, diffclk = False):
clk = "multiCLK[0]"
multiclk = "multiCLK"
if diffclk:
clk = "multiCLK2[0]"
multiclk = "multiCLK2"
try:
v = global_setting_dev_clk[id + 1]
clk = "multiCLK%d[0]"%(id + 1, )
multiclk = "multiCLK%d"%(id + 1, )
except:
pass
code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, )
+"\t.clock(%s),\n"%(clk, )
@@ -244,6 +252,12 @@ def __GenDevice(id, TerminateNode = False, diffclk = False):
return code_device
def __gen_slv_dev_predef(num):
global global_setting_dev_clk
code_for_clk = ""
for k in global_setting_dev_clk:
code_for_clk = code_for_clk + "reg [15:0] multiCLK%d;\n"%(k, )
code_predef =("`define DEV_NUM %d //slave num\n"%(num, )
+"`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master\n"
+"`define SPI_CSN_NUM (`ALL_DEV_NUM * 3)\n"
@@ -289,7 +303,7 @@ def __gen_slv_dev_predef(num):
gen_file_def = "dev_predef"
code = code_predef + code_qspi_mux_init + code_spi_mux_init
code = code_for_clk + code_predef + code_qspi_mux_init + code_spi_mux_init
genPkt.addAfterExc(code)
@@ -336,10 +350,7 @@ def gen_slv_dev_for_clk(num):
code = ""
for id in range(num - 1):
if id == 1:
code = code + __GenDevice(id, diffclk = True)
else:
code = code + __GenDevice(id)
code = code + __GenDevice(id)
code = code + __GenDevice(num - 1, True)
@@ -348,6 +359,48 @@ def gen_slv_dev_for_clk(num):
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
def set_dev_clk(cfg):
global global_setting_dev_clk
global_setting_dev_clk = cfg
code_for_clk = ""
for k in global_setting_dev_clk:
v = global_setting_dev_clk[k]
ph = int(8 * 1000000 * v[0] / 360.0)
period = int(1000000 + v[1])
code_for_clk = code_for_clk + __gen_slv_clk(k, ph, period)
genPkt = GenPkt()
genPkt.clean()
gen_file_def = "slave_dev_clk"
genPkt.addAfterExc(code_for_clk)
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
def __gen_slv_clk(clk, ph, period):
slv_code =(
""
#"\tinitial begin\n"
#+"\t\tforever begin #%d clock%d <= ~clock%d; end\n"%(period * 8, clk, clk)
#+"\tend\n\n"
+"\tgenerate\n"
+"\tfor( genvar i = 0; i < 16; i = i + 1 ) begin\n"
+"\t\tinitial begin\n"
+ "\t\t\t//相位信息\n"
+ "\t\t\t#%d\n"%(ph)
+ "\t\t\tmultiCLK%d[i] = 0;\n"%(clk, )
+ "\t\t\tfor( integer j = 0; j < i; j = j + 1 ) begin\n"
+ "\t\t\t\t#%d\n"%(period, )
+ "\t\t\t\t;\n"
+ "\t\t\tend\n"
+ "\t\t\tforever begin #%d multiCLK%d[i] <= ~multiCLK%d[i]; end\n"%(period * 8, clk, clk)
+"\t\tend\n"
+"\tend\n"
+"\tendgenerate\n")
return slv_code
def teardown():
#add_tc_2_runlist("")

33
tb/shinTest/testcase/rwregs.py
View File

@@ -1,21 +1,32 @@
from pyutils import *
from .environment import *
import time
import random
def tc1():
random.seed(int(time.time() * 1000))
genPkt = GenPkt()
#-------------------------------------------------------------------------
#>>>>>>嗅探数据包1，正常的嗅探数据包
genPkt.clean()
genPkt.setPktType(1)
gen_file_def = "regtest_tc01"
sm_idx = 0
tc_des = "测试寄存器的读写状态，将系统改为8B10B进行通信\\n"
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
+genWriteTransPktCode(gen_file_def, sm_idx)
+genTrgTransPktCode(gen_file_def, sm_idx)
+genReadAckPktCode(gen_file_def, sm_idx))
genPkt = GenPkt()
genPkt.clean()
dev_num = get_slv_dev_num()
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
change_8b10b_code = ""
for i in range(dev_num + 1):
change_8b10b_code = change_8b10b_code + genIFRwDataCode(i, 0x004c, True, 2, [0x1, 0x59])\
+genIFRwDataCode(i, 0x004c, False, 2)
genPkt.addAfterExc(#genWriteTransLenCode(gen_file_def, sm_idx)
#+genWriteTransPktCode(gen_file_def, sm_idx)
#+genTrgTransPktCode(gen_file_def, sm_idx)
#+genReadAckPktCode(gen_file_def, sm_idx)
change_8b10b_code
+genTcEndFrameCode(gen_file_def))
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
return gen_file_def