From 9c43daf51eda11a312372e1fb2a7e344052c51a8 Mon Sep 17 00:00:00 2001 From: bacon Date: Mon, 8 Sep 2025 16:47:30 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=BA=E5=A4=9A=E7=9B=B8=E4=BD=8D=E6=A8=A1?= =?UTF-8?q?=E6=8B=9F=E5=A2=9E=E5=8A=A0=E5=91=BD=E4=BB=A4=E8=A1=8C,?= =?UTF-8?q?=E5=A2=9E=E5=8A=A08b10b=E5=88=87=E6=8D=A2=E7=9A=84=E6=B5=8B?= =?UTF-8?q?=E8=AF=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 8 +-- tb/shinTest/Makefile_vcs | 26 ++++++++-- tb/shinTest/ShinTopSpiTb.v | 2 +- tb/shinTest/ShinTopSpiTb_clk.v | 13 ++--- tb/shinTest/gen_pkt_clk.py | 29 +++++++++++ tb/shinTest/testcase/base.py | 10 ++-- tb/shinTest/testcase/environment.py | 75 ++++++++++++++++++++++++----- tb/shinTest/testcase/rwregs.py | 33 ++++++++----- 8 files changed, 155 insertions(+), 41 deletions(-) diff --git a/Makefile b/Makefile index 857268e..bf694ad 100644 --- a/Makefile +++ b/Makefile @@ -41,7 +41,7 @@ shin: sbt "test:runMain test.testShinModule" testShin: - ./tb/shinTest/gen_pkt.py + python3 ./tb/shinTest/gen_pkt.py mkdir -p generated/log rm -rf generated/log/* iverilog -Wall \ @@ -52,10 +52,10 @@ testShin: -D IVERILOG_COMPILE \ ./tb/shinTest/ShinTopSpiTb.v vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true - ./tb/shinTest/check_testcase.py + python3 ./tb/shinTest/check_testcase.py testShinClk: - ./tb/shinTest/gen_pkt_clk.py + python3 ./tb/shinTest/gen_pkt_clk.py --dev1 0 200 mkdir -p generated/log rm -rf generated/log/* iverilog -Wall \ @@ -66,7 +66,7 @@ testShinClk: -D IVERILOG_COMPILE \ ./tb/shinTest/ShinTopSpiTb_clk.v vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true - ./tb/shinTest/check_testcase.py + python3 ./tb/shinTest/check_testcase.py testCDR: iverilog -Wall \ diff --git a/tb/shinTest/Makefile_vcs b/tb/shinTest/Makefile_vcs index afe16e2..1271f81 100644 --- a/tb/shinTest/Makefile_vcs +++ b/tb/shinTest/Makefile_vcs @@ -24,12 +24,32 @@ testShin_vcs: testShinClk_vcs: - python3 ./shinTest/gen_pkt_clk.py + python3 ./shinTest/gen_pkt_clk.py --dev1 0 90 --dev2 0 -90 mkdir -p generated/log rm -rf generated/log/* ${VCS} -f ./shinTestClk_vcs.f ${SIM} python3 ./shinTest/check_testcase.py + mv spi_trans_data.txt generated/spi_trans_data1.txt + mv generated/wave.vcd generated/wave1.vcd + \ + python3 ./shinTest/gen_pkt_clk.py --dev1 45 180 --dev3 25 -180 + mkdir -p generated/log + rm -rf generated/log/* + ${VCS} -f ./shinTestClk_vcs.f + ${SIM} + python3 ./shinTest/check_testcase.py + mv spi_trans_data.txt generated/spi_trans_data2.txt + mv generated/wave.vcd generated/wave2.vcd + \ + python3 ./shinTest/gen_pkt_clk.py --dev1 45 190 --dev3 25 -190 + mkdir -p generated/log + rm -rf generated/log/* + ${VCS} -f ./shinTestClk_vcs.f + ${SIM} + python3 ./shinTest/check_testcase.py + mv spi_trans_data.txt generated/spi_trans_data3.txt + mv generated/wave.vcd generated/wave3.vcd testShinMany_vcs: @@ -58,7 +78,7 @@ testShin: ./shinTest/check_testcase.py testShinClk: - ./shinTest/gen_pkt_clk.py + ./shinTest/gen_pkt_clk.py --dev1 0 200 mkdir -p generated/log rm -rf generated/log/* iverilog -Wall \ @@ -77,4 +97,4 @@ fstShinClk: gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 & clean: - rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* + rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.* diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 810a845..7e3b5ad 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -442,7 +442,7 @@ begin `ifdef VCS_COMPILE $dumpfile("./generated/wave.vcd"); //生成的vcd文件名称 - $dumpvars(0, ShinTopSpiTb);//tb模块名称 + //$dumpvars(0, ShinTopSpiTb);//tb模块名称 $dumpvars(0, ShinTopSpiTb.s_ShinTop_Mst);//tb模块名称 //$dumpvars(0, ShinTopSpiTb.s_ShinTop_slv124);//tb模块名称 //$dumpvars(0, ShinTopSpiTb.s_ShinTop_slv125);//tb模块名称 diff --git a/tb/shinTest/ShinTopSpiTb_clk.v b/tb/shinTest/ShinTopSpiTb_clk.v index 509dbeb..552f58c 100644 --- a/tb/shinTest/ShinTopSpiTb_clk.v +++ b/tb/shinTest/ShinTopSpiTb_clk.v @@ -12,13 +12,6 @@ module ShinTopSpiTb( reg [15:0] multiCLK; - reg clock2; - reg [15:0] multiCLK2; - - reg clock3; - reg [15:0] multiCLK3; - - `include "dev_predef.vh" `ifdef DEFINE_SLAVE_DEVICE @@ -361,7 +354,6 @@ ShinTop s_ShinTop_slv3( initial begin clock = 0; - clock2 = 0; reset = 1; latch0 = 0; @@ -407,6 +399,8 @@ generate end endgenerate + +/* //如果频率差到 80ppm，参数是： 8000640/1000080/8000640 [pass] //如果频率差到120ppm，参数是： 8000960/1000120/8000960 [pass] //如果频率差到160ppm，参数是： 8001280/1000160/8001280 [pass] @@ -466,8 +460,11 @@ generate end end endgenerate +*/ +`include "slave_dev_clk.vh" + initial begin spidata_file = $fopen("spi_trans_data.txt", "w"); diff --git a/tb/shinTest/gen_pkt_clk.py b/tb/shinTest/gen_pkt_clk.py index de1b418..b460137 100755 --- a/tb/shinTest/gen_pkt_clk.py +++ b/tb/shinTest/gen_pkt_clk.py @@ -2,11 +2,40 @@ #encoding=utf-8 from pyutils import * from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac +import argparse if __name__ == '__main__': + + parser = argparse.ArgumentParser() + + # 可选参数 + parser.add_argument("-d1", "--dev1", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm") + parser.add_argument("-d2", "--dev2", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm") + parser.add_argument("-d3", "--dev3", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm") + parser.add_argument("-d4", "--dev4", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm") + # 解析参数 + args = parser.parse_args() + # 使用参数 + dev_clk_info = dict() + if args.dev1 != [0, 0]: + dev_clk_info[1] = args.dev1 + + if args.dev2 != [0, 0]: + dev_clk_info[2] = args.dev2 + + if args.dev3 != [0, 0]: + dev_clk_info[3] = args.dev3 + + if args.dev4 != [0, 0]: + dev_clk_info[4] = args.dev4 + + environment.set_dev_clk(dev_clk_info) + environment.gen_slv_dev_for_clk(4) environment.bringup() + rwregs.tc1() + #add_tc_2_runlist(errorPkt.tc1()) #add_tc_2_runlist(errorPkt.tc2()) #add_tc_2_runlist(errorPkt.tc3()) diff --git a/tb/shinTest/testcase/base.py b/tb/shinTest/testcase/base.py index a09d142..5d5b73a 100644 --- a/tb/shinTest/testcase/base.py +++ b/tb/shinTest/testcase/base.py @@ -2337,9 +2337,13 @@ def tc28(): +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(4, 0x74, False, 4) - +genMessageCode("--读取中断使能") - +genIFRwDataCode(0, 0x70, False, 4) - +genIFRwDataCode(4, 0x70, False, 4) + +genMessageCode("--配置中断") + #+genIFRwDataCode(0, 0x70, False, 4) + #+genIFRwDataCode(4, 0x70, False, 4) + +genIFRwDataCode(0, 0x70, True, 4, [0x03, 0x00, 0x00, 0xf0]) + +genIFRwDataCode(4, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0]) + +genIFRwDataCode(0, 0x7c, True, 2, [0x10, 0x80]) + +genIFRwDataCode(4, 0x7c, True, 2, [0x10, 0x80]) +genMessageCode("--配置主从站") +genIFRwDataCode(0, 0x00, True, 1, [0x01, ]) diff --git a/tb/shinTest/testcase/environment.py b/tb/shinTest/testcase/environment.py index 4c60620..cc717c2 100644 --- a/tb/shinTest/testcase/environment.py +++ b/tb/shinTest/testcase/environment.py @@ -2,6 +2,9 @@ from pyutils import * global_dev_num = 4 +global_setting_dev_clk = dict() + + def bringup(): gen_file_def = "sys_bringup" @@ -177,7 +180,8 @@ def bringup(): add_tc_2_runlist(gen_file_def) -def __GenDevice(id, TerminateNode = False, diffclk = False): +def __GenDevice(id, TerminateNode = False): + global global_setting_dev_clk dout_code = "dDat_w[%d]"%(id + 1, ) din_code = "uDat_w[%d]"%(id + 1, ) if TerminateNode: @@ -186,9 +190,13 @@ def __GenDevice(id, TerminateNode = False, diffclk = False): clk = "multiCLK[0]" multiclk = "multiCLK" - if diffclk: - clk = "multiCLK2[0]" - multiclk = "multiCLK2" + try: + v = global_setting_dev_clk[id + 1] + clk = "multiCLK%d[0]"%(id + 1, ) + multiclk = "multiCLK%d"%(id + 1, ) + except: + pass + code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, ) +"\t.clock(%s),\n"%(clk, ) @@ -244,6 +252,12 @@ def __GenDevice(id, TerminateNode = False, diffclk = False): return code_device def __gen_slv_dev_predef(num): + + global global_setting_dev_clk + code_for_clk = "" + for k in global_setting_dev_clk: + code_for_clk = code_for_clk + "reg [15:0] multiCLK%d;\n"%(k, ) + code_predef =("`define DEV_NUM %d //slave num\n"%(num, ) +"`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master\n" +"`define SPI_CSN_NUM (`ALL_DEV_NUM * 3)\n" @@ -289,7 +303,7 @@ def __gen_slv_dev_predef(num): gen_file_def = "dev_predef" - code = code_predef + code_qspi_mux_init + code_spi_mux_init + code = code_for_clk + code_predef + code_qspi_mux_init + code_spi_mux_init genPkt.addAfterExc(code) @@ -336,18 +350,57 @@ def gen_slv_dev_for_clk(num): code = "" for id in range(num - 1): - if id == 1: - code = code + __GenDevice(id, diffclk = True) - else: - code = code + __GenDevice(id) + code = code + __GenDevice(id) code = code + __GenDevice(num - 1, True) genPkt.addAfterExc(code) genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) - - + + +def set_dev_clk(cfg): + global global_setting_dev_clk + global_setting_dev_clk = cfg + + code_for_clk = "" + for k in global_setting_dev_clk: + v = global_setting_dev_clk[k] + ph = int(8 * 1000000 * v[0] / 360.0) + period = int(1000000 + v[1]) + code_for_clk = code_for_clk + __gen_slv_clk(k, ph, period) + + genPkt = GenPkt() + genPkt.clean() + gen_file_def = "slave_dev_clk" + genPkt.addAfterExc(code_for_clk) + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + +def __gen_slv_clk(clk, ph, period): + slv_code =( + "" + #"\tinitial begin\n" + #+"\t\tforever begin #%d clock%d <= ~clock%d; end\n"%(period * 8, clk, clk) + #+"\tend\n\n" + + +"\tgenerate\n" + +"\tfor( genvar i = 0; i < 16; i = i + 1 ) begin\n" + +"\t\tinitial begin\n" + + "\t\t\t//相位信息\n" + + "\t\t\t#%d\n"%(ph) + + "\t\t\tmultiCLK%d[i] = 0;\n"%(clk, ) + + "\t\t\tfor( integer j = 0; j < i; j = j + 1 ) begin\n" + + "\t\t\t\t#%d\n"%(period, ) + + "\t\t\t\t;\n" + + "\t\t\tend\n" + + "\t\t\tforever begin #%d multiCLK%d[i] <= ~multiCLK%d[i]; end\n"%(period * 8, clk, clk) + +"\t\tend\n" + +"\tend\n" + +"\tendgenerate\n") + + return slv_code def teardown(): #add_tc_2_runlist("") diff --git a/tb/shinTest/testcase/rwregs.py b/tb/shinTest/testcase/rwregs.py index 9e0d9d8..036f988 100644 --- a/tb/shinTest/testcase/rwregs.py +++ b/tb/shinTest/testcase/rwregs.py @@ -1,21 +1,32 @@ from pyutils import * +from .environment import * + import time import random def tc1(): - random.seed(int(time.time() * 1000)) - genPkt = GenPkt() - - #------------------------------------------------------------------------- - #>>>>>>嗅探数据包1，正常的嗅探数据包 - genPkt.clean() - genPkt.setPktType(1) gen_file_def = "regtest_tc01" sm_idx = 0 + tc_des = "测试寄存器的读写状态，将系统改为8B10B进行通信\\n" - genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) - +genWriteTransPktCode(gen_file_def, sm_idx) - +genTrgTransPktCode(gen_file_def, sm_idx) - +genReadAckPktCode(gen_file_def, sm_idx)) + genPkt = GenPkt() + genPkt.clean() + + dev_num = get_slv_dev_num() + + genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)) + + change_8b10b_code = "" + for i in range(dev_num + 1): + change_8b10b_code = change_8b10b_code + genIFRwDataCode(i, 0x004c, True, 2, [0x1, 0x59])\ + +genIFRwDataCode(i, 0x004c, False, 2) + + + genPkt.addAfterExc(#genWriteTransLenCode(gen_file_def, sm_idx) + #+genWriteTransPktCode(gen_file_def, sm_idx) + #+genTrgTransPktCode(gen_file_def, sm_idx) + #+genReadAckPktCode(gen_file_def, sm_idx) + change_8b10b_code + +genTcEndFrameCode(gen_file_def)) genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) return gen_file_def