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增加从站回环的代码，仅加了一个，但是仿真结果有错误，需要检查

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This commit is contained in:
bacon
2025-02-10 00:03:16 +08:00
parent fd74e07123
commit 9943b5c044
6 changed files with 273 additions and 501 deletions
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39
tb/sw/tl2cdr/tl2cdr.h
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@@ -7,28 +7,6 @@
#define TL2CDR_BASE 0x10000000U
#define OLD_CODE
#ifdef OLD_CODE
#define CDR_ReadStatus 0x00U
#define CDR_WriteTxLen 0x04U
#define CDR_WriteTxFifo 0x08U
#define CDR_WriteTransDir 0x0cU
#define CDR_WriteSoftReset 0x10U
#define CDR_ReadRxLen 0x18U
#define CDR_ReadRxFifo 0x1cU
#define CDR_ReadIsLast 0x20U
#define CDR_ReadTxCrc 0x24U
#define CDR_ReadRxCrc 0x28U
#define CDR_WriteLimitTimer 0x2cU
#define CDR_INT_TXEND 14U
#define CDR_INT_RXERROR 15U
#define CDR_INT_RXSTART 16U
#define CDR_INT_RXEND 17U
#endif
#define CDR_INT_TX0END 14U
#define CDR_INT_TX1END 15U
#define CDR_INT_RX0ERROR 16U
@@ -37,13 +15,11 @@
#define CDR_INT_RX1START 19U
#define CDR_INT_RX0END 20U
#define CDR_INT_RX1END 21U
#define CDR_INT_TX0_FIFO_DEQ 22U
#define CDR_INT_TX0_FIFO_DEQ 22U
#define CDR_INT_TX1_FIFO_DEQ 23U
#define CDR_INT_RX0_FIFO_ENQ 24U
#define CDR_INT_RX1_FIFO_ENQ 25U
#define TX0_WriteSoftReset 0x00U
#define TX0_WriteTxLen 0x04U
#define TX0_WriteTxFifo 0x08U
@@ -73,19 +49,6 @@
#ifndef __ASSEMBLER__
#ifdef OLD_CODE
extern volatile uint32_t * const cdr_status;
extern volatile uint32_t * const cdr_txLen;
extern volatile uint32_t * const cdr_txFifo;
extern volatile uint32_t * const cdr_direct;
extern volatile uint32_t * const cdr_softReset;
extern volatile uint32_t * const cdr_rxLen;
extern volatile uint32_t * const cdr_rxFifo;
extern volatile uint32_t * const cdr_IsLast;
extern volatile uint32_t * const cdr_rxCrc;
extern volatile uint32_t * const cdr_txCrc;
#endif
extern volatile uint32_t * const tx0_softReset;
extern volatile uint32_t * const tx0_txLen;
extern volatile uint32_t * const tx0_txFifo;