增加从站回环的代码，仅加了一个，但是仿真结果有错误，需要检查

2025-02-10 00:03:16 +08:00
parent fd74e07123
commit 9943b5c044
6 changed files with 273 additions and 501 deletions
--- a/tb/sw/src/mstStartup.S
+++ b/tb/sw/src/mstStartup.S
@@ -65,234 +65,3 @@ _prog_start:
 	call main

 	ecall
-
-
-#if 0
-
-.balign 32
-.section .trap_entry, "ax", %progbits
-trap_entry:
-
-	addi	sp,sp,-136
-	sw	ra,4(sp)
-	sw	sp,8(sp)
-	sw	gp,12(sp)
-	sw	tp,16(sp)
-	sw	t0,20(sp)
-	sw	t1,24(sp)
-	sw	t2,28(sp)
-	sw	s0,32(sp)
-	sw	s1,36(sp)
-	sw	a0,40(sp)
-	sw	a1,44(sp)
-	sw	a2,48(sp)
-	sw	a3,52(sp)
-	sw	a4,56(sp)
-	sw	a5,60(sp)
-#ifdef __RV32I_MARCH__
-	sw	a6,64(sp)
-	sw	a7,68(sp)
-	sw	s2,72(sp)
-	sw	s3,76(sp)
-	sw	s4,80(sp)
-	sw	s5,84(sp)
-	sw	s6,88(sp)
-	sw	s7,92(sp)
-	sw	s8,96(sp)
-	sw	s9,100(sp)
-	sw	s10,104(sp)
-	sw	s11,108(sp)
-	sw	t3,112(sp)
-	sw	t4,116(sp)
-	sw	t5,120(sp)
-	sw	t6,124(sp)
-#endif
-
-#if 0
-    csrr t0, mstatus            # 读取 mstatus 寄存器
-    andi t0, t0, ~(1 << 3)      # 清除 MIE 位 (全局中断禁用)
-    csrw mstatus, t0            # 写回 mstatus 寄存器
-#endif
-
-	call plic_handle
-
-#if 0
-	csrr t0, mstatus
-	ori t0, t0, 1<<3
-	csrw mstatus, t0
-#endif
-
-	lw	ra,4(sp)
-	lw	sp,8(sp)
-	lw	gp,12(sp)
-	lw	tp,16(sp)
-	lw	t0,20(sp)
-	lw	t1,24(sp)
-	lw	t2,28(sp)
-	lw	s0,32(sp)
-	lw	s1,36(sp)
-	lw	a0,40(sp)
-	lw	a1,44(sp)
-	lw	a2,48(sp)
-	lw	a3,52(sp)
-	lw	a4,56(sp)
-	lw	a5,60(sp)
-#ifdef __RV32I_MARCH__
-	lw	a6,64(sp)
-	lw	a7,68(sp)
-	lw	s2,72(sp)
-	lw	s3,76(sp)
-	lw	s4,80(sp)
-	lw	s5,84(sp)
-	lw	s6,88(sp)
-	lw	s7,92(sp)
-	lw	s8,96(sp)
-	lw	s9,100(sp)
-	lw	s10,104(sp)
-	lw	s11,108(sp)
-	lw	t3,112(sp)
-	lw	t4,116(sp)
-	lw	t5,120(sp)
-	lw	t6,124(sp)
-#endif
-	addi	sp,sp,136
-
-	mret
-
-#.macro define_const name, value
-#    .equ \name, \value
-#.endm
-## 使用宏定义常量
-#define_const CDR_INT_TXEND, 	14
-
-opt_trap_entry:
-
-	addi	sp,sp,-136
-
-	#sw	ra,4(sp)
-	#sw	sp,8(sp)
-	#sw	gp,12(sp)
-	#sw	tp,16(sp)
-
-	sw	t0,20(sp)
-	sw	t1,24(sp)
-	#sw	t2,28(sp)
-	sw	s0,32(sp)
-	sw	s1,36(sp)
-
-	#sw	a0,40(sp)
-	#sw	a1,44(sp)
-	#sw	a2,48(sp)
-	#sw	a3,52(sp)
-	#sw	a4,56(sp)
-	#sw	a5,60(sp)
-	#sw	a6,64(sp)
-	#sw	a7,68(sp)
-	#sw	s2,72(sp)
-	#sw	s3,76(sp)
-	#sw	s4,80(sp)
-	#sw	s5,84(sp)
-	#sw	s6,88(sp)
-	#sw	s7,92(sp)
-	#sw	s8,96(sp)
-	#sw	s9,100(sp)
-	#sw	s10,104(sp)
-	#sw	s11,108(sp)
-	#sw	t3,112(sp)
-	#sw	t4,116(sp)
-	#sw	t5,120(sp)
-	#sw	t6,124(sp)
-
-#if 0
-    csrr t0, mstatus            # 读取 mstatus 寄存器
-    andi t0, t0, ~(1 << 3)      # 清除 MIE 位 (全局中断禁用)
-    csrw mstatus, t0            # 写回 mstatus 寄存器
-#endif
-
-	lui	t1, %hi(plic_claim)		
-	lw	t0, %lo(plic_claim)(t1)	# t0 = &plic_claim
-
-	lw  t1, 0(t0)				# t1 = *plic_claim
-	sw  t1, 0(t0)				# *plic_claim = t1
-
-	li	s0, CDR_INT_TXEND		
-
-	bne t1, s0, 1f				#_if (t1 != s0) goto 1f	
-
-	lui	s0,%hi(flag_intTxEnd)	#_else
-	li	s1,1
-	sw	s1,%lo(flag_intTxEnd)(s0)
-	j 4f
-
-1:
-	li  s0, CDR_INT_RXERROR
-	bne t1, s0, 2f				#_if (t1 != s0) goto 2f
-
-	lui	s0,%hi(flag_intRxError)	#_else
-	li	s1,1
-	sw	s1,%lo(flag_intRxError)(s0)
-	j 4f
-2:
-	li  s0, CDR_INT_RXSTART
-	bne t1, s0, 3f				#_if (t1 != s0) goto 3f
-
-	lui	s0,%hi(flag_intRxStart)	#_else
-	li	s1,1
-	sw	s1,%lo(flag_intRxStart)(s0)
-	j 4f
-
-3:
-	li  s0, CDR_INT_RXEND
-	bne t1, s0, 4f				#_if (t1 != s0) goto 4f
-
-	lui	s0,%hi(flag_intRxEnd)	#_else
-	li	s1,1
-	sw	s1,%lo(flag_intRxEnd)(s0)
-
-4:
-#if 0
-	csrr t0, mstatus
-	ori t0, t0, 1<<3
-	csrw mstatus, t0
-#endif
-
-	#lw	ra,4(sp)
-	#lw	sp,8(sp)
-	#lw	gp,12(sp)
-	#lw	tp,16(sp)
-	
-	lw	t0,20(sp)
-	lw	t1,24(sp)
-	#lw	t2,28(sp)
-	lw	s0,32(sp)
-	lw	s1,36(sp)
-
-	#lw	a0,40(sp)
-	#lw	a1,44(sp)
-	#lw	a2,48(sp)
-	#lw	a3,52(sp)
-	#lw	a4,56(sp)
-	#lw	a5,60(sp)
-	#lw	a6,64(sp)
-	#lw	a7,68(sp)
-	#lw	s2,72(sp)
-	#lw	s3,76(sp)
-	#lw	s4,80(sp)
-	#lw	s5,84(sp)
-	#lw	s6,88(sp)
-	#lw	s7,92(sp)
-	#lw	s8,96(sp)
-	#lw	s9,100(sp)
-	#lw	s10,104(sp)
-	#lw	s11,108(sp)
-	#lw	t3,112(sp)
-	#lw	t4,116(sp)
-	#lw	t5,120(sp)
-	#lw	t6,124(sp)
-
-	addi	sp,sp,136
-
-	mret
-
-#endif
-