客户第一次测试版本

src/main/scala/backBoard/LocalRegisters.scala

@@ -17,10 +17,10 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
 
   val param = IO(Input( new ManualParamBundle ))
 
-  val statusPage = downReg(0)(3,0)
+  val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass )
   val statusP    = RegInit(false.B)
   val statusRF   = RegInit(false.B)
-  val statusPR   = Cat( downReg(1).extract(0), downReg(0).extract(7) )
+  val statusPR   = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass )
   val statusER   = RegInit(false.B)
   val statusLE   = RegInit(false.B)
 
@@ -30,11 +30,11 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
   upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) )
 
   when( statusPage === 15.U ){
-    upReg(2) := downReg(2)
-    upReg(3) := downReg(3)
+    upReg(2) := 0.U
+    upReg(3) := 0.U
 
-    upReg(4) := downReg(4)
-    upReg(5) := downReg(5)
+    upReg(4) := 0.U
+    upReg(5) := 0.U
 
     upReg(16) := param.vendorID(7,0)
     upReg(17) := param.vendorID(15,8)
@@ -156,13 +156,17 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
 
   for( j <- 0 until gp ) {
 
-    val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U )
+    val digitalFilter = RegInit( 1.U(8.W) )
+
+    when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
+      digitalFilter := downRegTemp(4+j)
+    }
 
     val digitalIn = Reg( Vec(8, Bool()) )
 
     when( statusPage === 0.U ){
       upReg(2+j) := Cat( digitalIn.reverse  )
-      upReg(4+j) := downReg(4+j)
+      upReg(4+j) := digitalFilter
     }