From 98ca3b1ab11da9ca1eef0465f4fca52c8dbed5da Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 16 Apr 2024 18:52:23 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=A2=E6=88=B7=E7=AC=AC=E4=B8=80=E6=AC=A1?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=89=88=E6=9C=AC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardSlv.scala | 16 ++++++++++----- src/main/scala/backBoard/LocalRegisters.scala | 20 +++++++++++-------- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index 12151de..7a871d6 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -39,7 +39,7 @@ abstract class BackBoardSlvBase extends Module{ io.lvds_up_dout := lvdsSlv.io.lvds_up_dout val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) - val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) + // val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) } @@ -57,15 +57,21 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => downCnt := 0.U } + val isCrcPass = lvdsSlv.io.downstream_rx_crc_valid & ~lvdsSlv.io.downstream_rx_crc_err + // when( lvdsSlv.io.downstream_rx_crc_valid ){ // when( ~lvdsSlv.io.downstream_rx_crc_err ){ - // downReg := downRegTemp + // for( i <- 1 until 32 ) { + // downReg(i) := downRegTemp(i) + // } // } // } - when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){ - downReg := downRegTemp - } + // when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){ + // for( i <- 1 until 32 ) { + // downReg(i) := downRegTemp(i) + // } + // } } diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index 79caca3..874ea19 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -17,10 +17,10 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown val param = IO(Input( new ManualParamBundle )) - val statusPage = downReg(0)(3,0) + val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass ) val statusP = RegInit(false.B) val statusRF = RegInit(false.B) - val statusPR = Cat( downReg(1).extract(0), downReg(0).extract(7) ) + val statusPR = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass ) val statusER = RegInit(false.B) val statusLE = RegInit(false.B) @@ -30,11 +30,11 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) ) when( statusPage === 15.U ){ - upReg(2) := downReg(2) - upReg(3) := downReg(3) + upReg(2) := 0.U + upReg(3) := 0.U - upReg(4) := downReg(4) - upReg(5) := downReg(5) + upReg(4) := 0.U + upReg(5) := 0.U upReg(16) := param.vendorID(7,0) upReg(17) := param.vendorID(15,8) @@ -156,13 +156,17 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => for( j <- 0 until gp ) { - val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U ) + val digitalFilter = RegInit( 1.U(8.W) ) + + when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ + digitalFilter := downRegTemp(4+j) + } val digitalIn = Reg( Vec(8, Bool()) ) when( statusPage === 0.U ){ upReg(2+j) := Cat( digitalIn.reverse ) - upReg(4+j) := downReg(4+j) + upReg(4+j) := digitalFilter }