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客户第一次测试版本

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RuigeLee
2024-04-16 18:52:23 +08:00
parent 8040a20f6e
commit 98ca3b1ab1
2 changed files with 23 additions and 13 deletions
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16
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -39,7 +39,7 @@ abstract class BackBoardSlvBase extends Module{
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
// val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
}
@@ -57,15 +57,21 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
downCnt := 0.U
}
val isCrcPass = lvdsSlv.io.downstream_rx_crc_valid & ~lvdsSlv.io.downstream_rx_crc_err
// when( lvdsSlv.io.downstream_rx_crc_valid ){
// when( ~lvdsSlv.io.downstream_rx_crc_err ){
// downReg := downRegTemp
// for( i <- 1 until 32 ) {
// downReg(i) := downRegTemp(i)
// }
// }
// }
when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){
downReg := downRegTemp
}
// when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){
// for( i <- 1 until 32 ) {
// downReg(i) := downRegTemp(i)
// }
// }
}